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How to find gate count or area of a module in synthesized gate level netlist

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tariq786

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Hi folks,

I have an RTL design. I synthesized the design using Synopsys Design Compiler tool. I preserved the hierarchy during synthesis which means the synthesized gate level netlist has the same modular hierarchy that is in RTL design.

Now if i want to find the gate count or area of a particular module in the synthesized gate level netlist, how can i find that in Design Compiler?

Thanks

Kind Regards
 

I found it. It is

report_area -hierarchy

in synopsys design compiler.
 
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