difference bwtween delay cell and buffer layout

A buffer is used to fix tran violations in general. So layout wise what would you consider while making such cells

Would a delay cell which is used to fix hold just delay the waveform or would it also increase the slope from 0 to 1

vivekrajeev said:

A buffer is used to fix tran violations in general. So layout wise what would you consider while making such cells

Would a delay cell which is used to fix hold just delay the waveform or would it also increase the slope from 0 to 1

Click to expand...

In such case we use high drive strength buffers which will be helpful in reducing slew rate(0-1 or 1-0 transition time), because in such buffers drain and source widths will be increased compared to normal cells, then those cells will drive high currents..hope you understand

hey i understood frm your reply that a cell which is used to fix tran should have drain and source widths increased. Would you increase the gate size also here ???

And what about delay cells how are they made different from buffers in layout ???

Delay cells are used to fix hold violations in general.. Buffers as far as in your case need to be able to restore the slew degradation and hence have higher drive strength.
Increasing gate width reduces gate capacitance hence reduces delay, but results in higher leakage..Delay cells are also buffer cells but with slower transition time.

jeevan.life said:

Delay cells are used to fix hold violations in general.. Buffers as far as in your case need to be able to restore the slew degradation and hence have higher drive strength.
Increasing gate width reduces gate capacitance hence reduces delay, but results in higher leakage..Delay cells are also buffer cells but with slower transition time.

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sharif.shiek said:

In such case we use high drive strength buffers which will be helpful in reducing slew rate(0-1 or 1-0 transition time), because in such buffers drain and source widths will be increased compared to normal cells, thenthose cells will drive high currents..hope you understand

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@ Sharif.shiek: High drive strength buffers have wider channel. Drain and source has nothing to do with the current capability of the cell. Drain and source are used to provide contacts. Drain and source are highly dopped to obtain a good ohmic contact.

@Jeevan.life: Increasing the gate width will increase the gate capacitance as capacitance is directly proportional to area. But it increases the cell's driving capability. If you MOSFET drain current equation drain current is directly proportional to channel width. So increasing the gate width will increase the cell driving capability and also increase its input capacitance.



MOSFET - Wikipedia, the free encyclopedia

Now coming to delay cells. Architecture of delay cells may vary from library to library. I checked delay cells in TSMC 40nm library. Delay cells in this library have delay starting from 20ps to few Nano seconds!!! Delay cells having small delay were same as normal buffers. But delay cells having larger delay are not simple buffers. They have different kind of circuit inside. It has inverter in input and a inverter in output and in between these two inverters it has a combination of a inverter and pass transistors. Pair of inverter and pass transistor provide at large delay. Depending on the delay of the cell, pair of inverter and pass transistor can be repeated multiple times. If you wants to see open your spice file of library. You also check area of delay cells having large delay. It will have area much greater than normal buffers.

@Jeevan.life: Increasing the gate width will increase the gate capacitance as capacitance is directly proportional to area. But it increases the cell's driving capability. If you MOSFET drain current equation drain current is directly proportional to channel width. So increasing the gate width will increase the cell driving capability and also increase its input capacitance.



MOSFET - Wikipedia, the free encyclopedia

Now coming to delay cells. Architecture of delay cells may vary from library to library. I checked delay cells in TSMC 40nm library. Delay cells in this library have delay starting from 20ps to few Nano seconds!!! Delay cells having small delay were same as normal buffers. But delay cells having larger delay are not simple buffers. They have different kind of circuit inside. It has inverter in input and a inverter in output and in between these two inverters it has a combination of a inverter and pass transistors. Pair of inverter and pass transistor provide at large delay. Depending on the delay of the cell, pair of inverter and pass transistor can be repeated multiple times. If you wants to see open your spice file of library. You also check area of delay cells having large delay. It will have area much greater than normal buffers.[/QUOTE]


Thanks Yadav, Cleared one of my concepts :smile:

@yadav

thanks boss cleared many of my doubts thanks for the detalied rely