Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Synopsys DC warning (TIM-111)

Status
Not open for further replies.
S

soloktanjung

Full Member level 6
Joined
Nov 20, 2006
Messages
364
Helped
51
Reputation
100
Reaction score
43
Trophy points
1,308
Location
nowhere
Activity points
3,194
Hello,

My design has 2 different and independent clocks. So I constraint it using:

Code: 
set_clock_groups -async -group clock1 -group clock2
set_ideal_network [get_ports clock1]
set_ideal_network [get_ports clock2]

After loading the constraints, I got this warning:

Warning: Clock port 'clock1' is assigned input delay relative to clock 'clock2'. (TIM-111)
Click to expand...

My question is: should I care about the warning? Is it important for timing accuracy?

Thank you.

Hairo
 

Code: 
man TIM-111
DESCRIPTION
       This issue will be issued when setting an input delay  on  clock  port,
       and it is not specified relative to the same clock.
WHAT NEXT
       Remove the unneeded input delay value using the remove_input_delay com-
       mand.
 
Thank you for the reply. I'm still not able to solve the warning.


First I did like this:

Code: 
set_input_delay 2 -max -clock clock1 [all_inputs] 
set_input_delay 0.1 -min -clock clock1 [all_inputs]

set_input_delay 2 -max -clock clock2 [all_inputs]
set_input_delay 0.1 -min -clock clock2 [all_inputs]


Then I changed the input delay constraint like this:

Code: 
set_input_delay 2 -max -clock clock1 [remove_from_collection [all_inputs] [get_ports clock1]]
set_input_delay 0.1 -min -clock clock1 [remove_from_collection [all_inputs] [get_ports clock1]]

set_input_delay 2 -max -clock clock2 [remove_from_collection [all_inputs] [get_ports clock2]]
set_input_delay 0.1 -min -clock clock2 [remove_from_collection [all_inputs] [get_ports clock2]]


And the warning is still there.

I don't know why should I use remove_input_delay since it will remove input delay constraint on the specific input ports.
Please anyone advice me.

Thank in advance.

Hairo
 

It should be like

set_input_delay 2 -max -clock clock1 [remove_from_collection [all_inputs] [get_ports clock2]]
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top