adder with register (latch)

hii....i really need someone to help me to check this code....i'm try to built an adder with register feedback as you can see in the diagram below. here is my code of program and the testbench code...There's no error on the code unfortunately the waveform doesn't appear as I wish...the test bench code is work cause I'd test it before with the other program..It's probably because of the code of program where there are errors which I can't detect it...kindly please check this for me because I'm out of idea...=)

Without telling us what the problem is, there is no way we can see whats wrong.

Did you also mean to build it asynchronously (ie. without a clock?). This will not work too great on an FPGA.

PS. you are allowed to use integers in ports (and it means you dont have to do type conversions all over the place!)

I can see 1 error

wire3 <= ((wire2(n-1 downto 0) ) + (2**n - select_mod)) when(wire1 or wire2) = '1' else wire2;

n=3 and select_mod=5 so it becomes

wire3 <= ((wire2(2 downto 0) ) + (3)) when (wire1(3) or wire2(3)) = '1' else wire2;

the error you are getting is because you are assigning a 3bit signal (2 downto 0) to a 4 bit signal (3 downto 0)

depending on what you want to do you can either do
wire3 <= (('0'&wire2(n-1 downto 0) ) + (2**n - select_mod)) when(wire1 or wire2) = '1' else wire2;
or
wire3 <= '0'&((wire2(n-1 downto 0) ) + (2**n - select_mod)) when(wire1 or wire2) = '1' else wire2;
or
wire3 <= ((wire2(n downto 0) ) + (2**n - select_mod)) when(wire1 or wire2) = '1' else wire2;

Alex

thanks....it's work..but I need to include the latch register in this code....

this line should be the latch register...but i don't know how to insert the latch register in here....
wire2 <= ('0' & wire1 (n-1 downto 0));

again...really need u guys to help me....=)

I don't understand what exactly you are trying to do, i don't understand the chart very well.
suppose that a=111 and b=100

wire1 <= (('0' & unsigned(a)) + ('0'& unsigned(b))); -- 1011 = 0&111 + 0&100

wire2 <= ('0' & wire1 (n-1 downto 0)); -- 0011 = 0&011
wire2 will always be 0, why do you check if it is 1 in the next line?

wire3 <= ((wire2(n-1 downto 0) ) + (2**n - select_mod)) when(wire1 or wire2) = '1' else wire2;
result is 011+(2^3 -5) else 0011

c <= std_logic_vector(wire3(n-1 downto 0));
the result is only the last 3 bits of wire3 so why do you declare it as 4bit signal?

Alex

I have to do the VHDL code for the diagram which mean I have to convert the schematic to the VHDL code. It's a generic and modulus adder which involve a latch register feedback as you can see diagram. As example, n = 3 which it will be 3 bit signal and the mod is 5 where the program will be count from 0 --> 4 only...If let say a+b = 5, it will count to 0 back.......Ohh, sorry...I forget to label the diagram. Maybe this diagram helps to explain why I'm declaring the wire for each components as 4bits...


so whenever the total input a+b >= select_mod, it will do the value in latch will be feedback to do the second cycle of operation which it will add with 2^n-m..as example...if the total a+b is 5...in the second cycle it will add with 2^n - m which is 3...so 101 + 011 = 1000...therefore the value for the MSB will be the wire1 = 1 and the output for this will be 000....my problem is I don't know how to insert the latch code in this program...thanks again for the help...=)

The code you posted contains no latches or registers, only logic.

To create a latch you need to put code into a process with an enable signal (or preferably a clock to make it synchronous)

Like this:


or you can create one with a "when" case without an else:
output <= some_logic when enable = '1';

having an else causes it to become logic, not a memory.

You probably need to use processes to make the sequential statements.

take a look VHDL Tutorial Sequential Statements

Alex