want to know about ncxlmode../ and cadence tools

Hi,

I'm new to cadence tools...To do simple simulation there are many options available.

So far i saw following tools..

ncverilog - to compile verilog files
ncvhdl - to compile VHDL files
ncsim - for simulation
ncxlmode - I dont know what is this but this complies verilog files, what is the differece/advantage over ncverilog.

Please add other tools available from cadance for digital design/verification.

It will help me and other to get overview of all tools from cadence.

thanks!

---------- Post added at 16:50 ---------- Previous post was at 16:34 ----------

I found another one "nclaunch" what is it?

new list
----------
ncverilog - to compile verilog files
ncvhdl - to compile VHDL files
ncsim - for simulation
ncxlmode - I dont know what is this but this complies verilog files, what is the differece/advantage over ncverilog.
"nclaunch"- what is it?

thanks!

Hi, as far as ncxlmode is concerned.

The ncverilog tool flow is to compile, elaborate, and simulate; three steps to get simulation results.

These three steps were very different from the standard (years ago) Verilog-XL flow; you just ran Verilog-XL with your RTL.

Ncxlmode just runs, looks, and feels like Verilog-XL. aka NC in Verilog-XL mode...

Some history:
A Verilog-XL run required parsing the RTL first and then simulating every time you ran a job; for large jobs it took a long time to get into simulation. you could save a snap-shot, but for very large sims this was not practical.

Along came compiled code simulators. This technology allowed the user to split the process up in order to save time. While there are some interactive capabilities in non-compiled code simulators that you don't get in compiled-code simulators, but the speed improvements associated with compiled-code simulators far out ways the loss of functionality.

Thanks for such great explanation....really good info!