[SOLVED] Question from a rookie:Why DC report violation of RN port ?

Hi,All:
I'm doing synthesize using DC, it report me a violation , who has a summary below:

point fanout cap trans incr path
clock clk_osc 0.00 0.00
.... .... .... .... .... ....
u_sys/dct_rstn_d2_reg/Q 0.11 0.29 1.09r
.... .... .... .... .... ....
u_sys/U16/A0 (OAI2BIX8M) 0.11 0.0 1.09r
u_sys/U16/Y (OAI2BIX8M) 0.21 0.16 1.26f
u_sys/n14 (net) 1 0.08 0.00 1.26f
u_sys/U17/A (INVX32M) 0.21 0.00 1.26f
u_sys/U17/A (INVX32M) 510.92 281.46# 282.71r
u_sys/dct_rst_n_out (net) 1972 1053.81 0.00 282.71r
.... .... .... .... .... ....
u_dct_ahb_top/u_ahb_top/u0_arbiter/hgrant_m1_reg/RN (SDFFRX4M)
510.92 0.00# 282.72r
data arrival time 282.72

clock clk_osc (rise edge) 8.00 8.00
clock network delay (ideal) 0.80 8.80
clock uncertainty -0.47 8.33
u_dct_ahb_top/u_ahb_top/u0_arbiter/hgrant_m1_reg/CK (SDFFRX4M) 0.00 8.33
library recovery time -47.45 -39.12
data required time -39.12
-------------------------------------------------------------------------------------------
slack(VIOLATED) -321.83

And the RTL code about the signal "u_sys/dct_rst_n_out" is :
always @ (posedge dct_clk_out or negedge chip_rst_n)
begin
if (chip_rst_n == 1'b0)
begin
dct_rst_n_d1 <= 1'b0;
dct_rst_n_d2 <= 1'b0;
end
else
begin
dct_rst_n_d1 <= 1'b1;
dct_rst_n_d2 <= dct_rst_n_d1 ;
end
end
assign dct_rst_n_out = test_mode? chip_rst_n:dct_rst_n_d2;

I thought i have a lot of question about this violation
1. What is the "library recovery time " for?
2. RN is asynchronous reset signal of DFF cell, we need to know it's arrive time ,and analyse it?
3. How should i eliminate this violation?
My head is chaotic now, Does anybody can help me ?
Thanks in advance.

Re: Question from a rookie:Why DC report violation of RN por

Concept of reset recovery time is similar to the setup time.
If you want the non-reset state to be in effect starting at some clock edge, you have to deassert the reset signal before this clock edge. If you deassert reset signal too close to the clock edge, non-reset state won't be effective right on this clock edge. How close is too close ? That is the reset recovery time. Basically, you have to deassert reset signal by the recovery time before the next clock edge so that non-reset state starts at that clock edge.

I think you have a huge fanout on one of the net and its delay is huge. I guess you didn't build a buffer tree for reset signal.
YOu have 2 options.
1. Let DC buffer the reset path. I don't remember well, but DC might have a fanout limit to build a buffer tree. TOo much fanout could make DC stop buffering and you may have to set some variable to increase this limit.
2. Don't even bother to build buffer tree on DC. Just set it ideal net(Ignore the timing) and dont_touch, and let backend tool to take care of buffering.

Whether you have to meet recovery time on async reset depends on your design, but most probably you have to to keep all the flops in sync when it comes out of reset state. That's the reason why you have synchronizers on reset path.

Hi,lostinxlation
It's you again. Thank you.

Now I knew what is the library recovery time now. But the delay is always positive, and the recovery time is always negative. In this case library recovery time is -47.45,with a clock period is just only 8,therefor the data required time is always negative too. So, I think it is impossible to meet the recovery time. right?

I set ideal network at port chip_rstn_pad, it works when chip_rst_n is derectly connected with dct_rst_n_out; when chip_rst_n is as an alternative of dct_rst_n_out, it doesn't work ,although i set dont_touch for it. The only thing I can do is buffer it ?

Regards.
oscillator_cn1

Re: Question from a rookie:Why DC report violation of RN por

You need to look at the .lib file and find out how much the recovery time of the flop actually is. Since you have a huge fanout on the reset net and slew on that net becomes extremely bad, DC is going to extrapolate the recovery time on the timing arc in the library. I'm sure if slew is a healthy number, recovery time shouldn't be that bad.

You should set ideal net on dct_rst_n_out.