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Question about toolflow

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mrtxyz

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Hello,

This is my first post in this forum and I don't have much experience with design tools. An here is my story why I'm here: At my university I have been working on a project to reduce power dissipation on the interconnect of a chip. Therefore i have designed a CO/DEC circuit at logic level in VHDL. Due to my theoretical calculations the circuit works fine and reduces the crosstalk effects on the links. This far, everything is fine.

Now i need to verify my solution with a simulation. I need to calculate power consumption and area overhead of my design. Using Xilinx tools is not possible because FPGAs are not suitable for inspecting low level effects such as crosstalk.

As i said before this is my first experience on this subject and need help to find a suitable tool. My input will be a 1).vhdl or .verilog, 2)a suitable library and 3)data transmitted on the interconnect, as output i'm expecting area and power characteristics of my design. What tools can you recommend me on this subject?

I have been looking forward to hearing from you. Any help will be greatly appreciated.

Thanks in advance
 

If you have access to synopsys design compiler and primetime/PX, it should do the job for you. synthesize the netlist with design compiler and read it into primetime/PX to get the power statistic information. You also need to have a library such as TSMC with library support for synopsys tools. I know all of TSMC standard libraries are characterized for power which is how synopsys tool calculates the power for your design.
 

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    mrtxyz

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Yes, i have access to the Synopsys DC and Primetime. I should better start learning these tools.

Thanks a lot, helped me very much in desperate times :D
 

furthermore, if you want to do power analysis, you can try to use low-power flow!
 

mrtxyz said:
Hello,

This is my first post in this forum and I don't have much experience with design tools. An here is my story why I'm here: At my university I have been working on a project to reduce power dissipation on the interconnect of a chip. Therefore i have designed a CO/DEC circuit at logic level in VHDL. Due to my theoretical calculations the circuit works fine and reduces the crosstalk effects on the links. This far, everything is fine.

Now i need to verify my solution with a simulation. I need to calculate power consumption and area overhead of my design. Using Xilinx tools is not possible because FPGAs are not suitable for inspecting low level effects such as crosstalk.

As i said before this is my first experience on this subject and need help to find a suitable tool. My input will be a 1).vhdl or .verilog, 2)a suitable library and 3)data transmitted on the interconnect, as output i'm expecting area and power characteristics of my design. What tools can you recommend me on this subject?

I have been looking forward to hearing from you. Any help will be greatly appreciated.

Thanks in advance
Click to expand...

Hi,
Try Synopsys DC compiler ....... dat will be best ......
 

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