Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Antenna violation questions (metal jogging, diode insertion)

Status
Not open for further replies.

jitendravlsi

Full Member level 2
Joined
Jul 21, 2008
Messages
132
Helped
8
Reputation
16
Reaction score
5
Trophy points
1,298
Activity points
2,136
antenna vilation

To remove antenna violation one has to do either metal jogging(jumping) or antenna diode insertion.

please tell me

1) On which parameters any body will decide whether he has to do metal jogging or diode insertion?
Does these instructions comes from top level designer?

2) Why we always do metal jogging to upper metal layers only, why not to lower layers?

3) What is the speciality of antenna diode? Is this the ordinary diode or some special diode?

4) If any body is facing antenna violation in top most layer say M8 then how will he remove this violation because then there is no option for metal jogging because M8 itself is topmost layer.
 

antenna vilation

i hav't wrked on antenna violation and fixing, but i have knowledge of it

1) preferable people will go for jogging to diode insertion,, if u r supplying any hard i/p then generally all inputs will be aded with antenna diodes as we dont know whts the input layer profile

3) its normal diode (made of transistor) in reverse biosed direction
4) why dont u jog to down layers
 

    jitendravlsi

    Points: 2
    Helpful Answer Positive Rating
Re: antenna vilation

Dear Raju,

there may be some reason for not jogging to lower layers, which I don't know.

may be somebody can explain....................

if thats the case then how can we remove antenna violation in query no 4)


btw thanks
 

Re: antenna vilation

Hi Jitu,

1) On which parameters any body will decide whether he has to do metal jogging or diode insertion? Does these instructions comes from top level designer?

If you want to know what is antenna violation ?, please go through a ASIC book or literature. that should help us to get the idea

which parameter decides : -> It is ratio of Metal area by Gate area of transistor. ( to know why, literature on ASIC should help u)

from where this comes : --> all the foundaries will give a rule deck for Antenna DRC violation. they will check the ratio (defined in above line) by coding it as rule in drc deck itself

2) Why we always do metal jogging to upper metal layers only, why not to lower layers?

Resistivity of lower layer will be high, so if we jog to lower layers , we will actually increase the resistance of the net, so by solving the problem of Antenna violation , we will tend to increase the delay of net. but jogging to higher layer will not increase net resistance.

3) What is the speciality of antenna diode? Is this the ordinary diode or some special diode?
nothing special, they are simple reverse biased diodes but made of transistors

4) If any body is facing antenna violation in top most layer say M8 then how will he remove this violation because then there is no option for metal jogging because M8 itself is topmost layer.

it cant be solved, that is why people dont use top metal for signal routing

Hope it helps u

Regards
Nav
 
Re: Antenna violation questions (metal jogging, diode insert

Dear Nav,

What I tried to ask is not answered by you.

1) On which parameters any body will decide whether he has to do metal jogging or diode insertion?


thanks
Jit
 

Re: Antenna violation questions (metal jogging, diode insert

One reason you might do metal jogging instead of diode insertion is if you're doing an ECO and you're not allowed to make any changes to the base layer and there aren't any spare cell antenna diodes lying around.
 

    jitendravlsi

    Points: 2
    Helpful Answer Positive Rating
Re: Antenna violation questions (metal jogging, diode insert

Thanks Denki,

one reason to insert diode may be the top metal layer, because for this metal layer we dont have the option to jog for higher metal layer so we can use antenna diode in this case.


any other reason to insert antenna diode?
what are the drawbacks of antenna diodes?
 

Re: Antenna violation questions (metal jogging, diode insert

presumable drawbacks i can think of off the top of my head:
1) area: antenna diodes take up area
2) speed: they add a diffusion capacitance to the net they're attached to
 

    jitendravlsi

    Points: 2
    Helpful Answer Positive Rating
1)On which parameters any body will decide whether he has to do metal jogging or diode insertion? Does these instructions comes from top level designer?

Antenna violation is not a functionality issue rather a DFM issue.
So its insertion is decided by back end engineer only.
It is better to go with metal jogging as we save std cell area.(if we have routing resource available)
But if it is too big and less chances to fix with metal jogging you can go for diode insertion. Now adays, PNR tool are able to handle this with out manual effort.

2) Why we always do metal jogging to upper metal layers only, why not to lower layers?
As you know, antenna violation causes gate(i/p of CMOS) damage by Electro Static Discharge(ESD), during layer by layer manufacuring of the chip.
So you can understand that by jogging to below layers you are not changing the conductor area in contact with that specific gate in question. It can be done only by changing to top layers..
Just think about the structure during layer by layer fabrication.

3) it is a normal diode as i know..
4) We will not get antenna viol in top layer because as the circuit is complete now, i/p pin is not isolated and CMOS o/p ckt works as a reverse biased diode to conduct any ESD if it comes.

Regards
-finny
 
hi Denki,

Please check the following Blog. It will help you a lot to understand about Antenna voilation reason and solution. Evevn After this if you thing that there are any unresolved query .. please let meknow.
VLSI Concepts: Antenna Effects
 

Antenna violation comes to picture only with a long metal strip connected to gate...During fabrication, lower metals are etched first...if I have a long M1 during CMP, charge can accumulate and can burn off the gate....so we chop M1 and put vias and connect to M2 strip (M2 should be close to the gate). This makes sure that charge accumulated doesnot reach the gate....
When we lay M2 during fab, Its just a small strip and the charge accumulated is not sufficient to damage the gate....
 

    V

    Points: 2
    Helpful Answer Positive Rating
Re: antenna vilation

Hai,

If any body find any antenna violation at the top most layer.... then preferably we will go for antenna diode insertion method

To solve antenna violation we will prefer jump to only the top most layers because during etching and Ion-Implantation process heavy charge will get accumulated into lower layers and then they may effect them.....

If we use top layer, the heavy charge will get discharged....

Thank You
T.Prasad
 

Re: Antenna violation questions (metal jogging, diode insert

if routing resources permits go for jogging. for adding diode you might move some cells. and may cause other drcs. ( not preferred at last stage of design when tape out is hanging on the head)
 

One more point.
If u have antenna violation on the top most layer only diodes can help u fix these violations.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top