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soc design order' problem

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HolySaint

HolySaint

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rtl(.v)---net(dc)---mbist(mbistarchitect)---dftc---tmax

is the flow ok?

and who can tell me how to convert db scripts to xg mode scripts (dc scripts)?
 

HolySaint said:
rtl(.v)---net(dc)---mbist(mbistarchitect)---dftc---tmax

is the flow ok?

and who can tell me how to convert db scripts to xg mode scripts (dc scripts)?
Click to expand...

the most commom flow is like this: if you are starting RTL--GDSII
functional rtl(.v) -->bist rtl geneartion/intergration into RTL--> pyhsical synthesis(includes scan insertion)(DC)--> ATPG pattern gen(Tmax).
 

    HolySaint

    HolySaint

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i use mbistarchitect to insert mbist
dc to design compile
dftc to insert scan chains
tmax to generate ATPG

when i insert mbist in rtl, shall i set mems dont tounch in dc?
 

HolySaint said:
i use mbistarchitect to insert mbist
dc to design compile
dftc to insert scan chains
tmax to generate ATPG

when i insert mbist in rtl, shall i set mems dont tounch in dc?
Click to expand...

irrespective of which tool use -- after inserting the BIST into RTL either read black box memory module for synthesis or say dont touch the memory modules.
 

    HolySaint

    HolySaint

    Points: 2
    Helpful Answer Positive Rating
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