omara007
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Hi folks
I want to implement a synthesizable verilog code or a function that returns an index of the first occurrence of digit '1' (or digit '0') in a vector. For example, if this is the vector :
reg [7:0] x;
x = 8'b0100_1111
the executioin of the function should return '6' if we start from MSB and should return '0' if we start from LSB.
I want to implement a synthesizable verilog code or a function that returns an index of the first occurrence of digit '1' (or digit '0') in a vector. For example, if this is the vector :
reg [7:0] x;
x = 8'b0100_1111
the executioin of the function should return '6' if we start from MSB and should return '0' if we start from LSB.