Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Maximum Stacked (series) Transistors?

Status
Not open for further replies.

torontograd

Newbie level 2
Joined
Mar 28, 2008
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,298
Hi all,

I am a bit confused by how to determine the maximum number of permissible serial transistors in a logic gate in 0.18 (or technology really). Is there a limit? My thought would be that if for example, the number of series PMOS is too great, Vout of the digital gate would not rise high enough to excite the NMOS of the next gate in the logic path.

For example: is it possible to create a 5-input NAND with 0.18 technology? How about a NOR? (series PMOS instead of NMOS). How about a 6- or 7-input gate? Where is the limit?

As an experiment, I have tried testing this in Cadence, for example creating a simple chain of 3 NMOS transistors, with a small capacitor with an initial vale of 1.8V on the top of the stack. Simulation shows that the capacitor is fully discharged through the NMOS chain, as opposed to only partially discharging to 1.8V - 3 * Vth.

Thanks for any help/clarifications you can provide!
 

torontograd said:
I am a bit confused by how to determine the maximum number of permissible serial transistors in a logic gate in 0.18 (or technology really). Is there a limit? My thought would be that if for example, the number of series PMOS is too great, Vout of the digital gate would not rise high enough to excite the NMOS of the next gate in the logic path.

No. In static CMOS, the transistors swing all the way to cut-off, so there is no Vt drop. You're thinking about Vt drops in analogue circuits where the stacked transistors are all kept in saturation.

For example: is it possible to create a 5-input NAND with 0.18 technology? How about a NOR? (series PMOS instead of NMOS). How about a 6- or 7-input gate? Where is the limit?
Yes, Yes, Yes, the limit is your target speed.

Are you sure you're really a University of Toronto grad student? ;p
 
What if he is a control systems (etc.) grad student. There is no reason to be caustic - being a grad student does not imply solid digital circuit skills.
 

Haha! Thanks for the comeback, and also thanks for the help roadbuster, much appreciated.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top