I want to determine what is the maximum operating frequency an RTL design can operate at, however, I am not sure how to do this. I know that one can calculate the maximum operating frequency from the Worst Negative Slack, but that is the max operating frequency for that particular synthesized design. How could this be done in a more generic case? I have thought about giving a very un-realistic clock frequency as a constraint and then the synthesis tool will probably try to synthesize the fastest possible logic. Is this approach correct? Is there some other standard approach to solve this issue?