# Maximum operating frequency

#### jagjordi

##### Newbie
I want to determine what is the maximum operating frequency an RTL design can operate at, however, I am not sure how to do this. I know that one can calculate the maximum operating frequency from the Worst Negative Slack, but that is the max operating frequency for that particular synthesized design. How could this be done in a more generic case? I have thought about giving a very un-realistic clock frequency as a constraint and then the synthesis tool will probably try to synthesize the fastest possible logic. Is this approach correct? Is there some other standard approach to solve this issue?

#### barry

##### Advanced Member level 5
Why specify an “unrealistic clock frequency”? Are you creating an unrealistic design? The maximum frequency depends on a lot of factors: placement, routing, technology, etc. Generally, engineers have a requirement and then create a design, not the other way around.
You could look at the parameters (e.g. clock-to-output propagation delay) of a flip flop and calculate max frequency from that, but that’s slightly naive.

#### jagjordi

##### Newbie
Why specify an “unrealistic clock frequency”? Are you creating an unrealistic design? The maximum frequency depends on a lot of factors: placement, routing, technology, etc. Generally, engineers have a requirement and then create a design, not the other way around.
You could look at the parameters (e.g. clock-to-output propagation delay) of a flip flop and calculate max frequency from that, but that’s slightly naive.
It is sort of an unrealistic design, I am comparing different implementations of a function and I want to compare their maximum operating frequency. I understand that it's not a realistic scenario but how do you suggest I perform the comparison? I don't have any requirement since its not a design that should be used in any product, just an experiment.

##### Super Moderator
Staff member
In general...

The design with the largest logic cones between flip-flop stages will be the slowest.

Adding more pipeline stages with smaller cones of logic between flip-flops will increase the maximum clock frequency.

Your "quest" for comparing implementations is unrealistic. You can pretty much tell by just looking at the logic between registers to determine if the design will be faster. The final determination is dependent on the placement and routing of the final netlist.

#### dick_freebird

##### Advanced Member level 5
There's a big difference between "let the
computer do the thinking" max clock rate
and "maximum effort".

As an example in the fiber optic engine I
sometimes mention, my in-house stdCellLib
would not self-toggle (D=Qb) reliably above
300MHz and my task was to take a 800MHz
input clock and make 400MHz clocks for
different domains, call it chip-scale, along
with clock recovery and SERDES running on
that clock (along with an 8-phase clock-field
from which RX clock was selected).

So I had to redesign all the logic gates myself
for higher speed operation, use LVT devices
in the flip-flops, pipeline the hell out of the
logic (breaking long logic chains into ones
that would fit in the clock period), create
"clock pullback" chains to deal with cases
where the logic could not get done in a
clock cycle and simulate the whole thing
in Spectre with veriloga "logic" models and
criticize the output against a set of "expect"
vectors with more veriloga widgets. In the
end it worked.

Sound like fun? It wasn't, to the tune of 3 years
of engineering from start to production parts.

But point is, what's "maximum" depends a lot
on how much burden you are willing, allowed,
and supported to shoulder.

#### ThisIsNotSam

##### Advanced Member level 5
I want to determine what is the maximum operating frequency an RTL design can operate at, however, I am not sure how to do this. I know that one can calculate the maximum operating frequency from the Worst Negative Slack, but that is the max operating frequency for that particular synthesized design. How could this be done in a more generic case? I have thought about giving a very un-realistic clock frequency as a constraint and then the synthesis tool will probably try to synthesize the fastest possible logic. Is this approach correct? Is there some other standard approach to solve this issue?
this approach is not correct. the tool will give up eventually because it will realise the problem is not feasible. it will also buffer all paths unnecessarily. what you have to do is to apply engineering skills: start from a reasonable frequency and adjust accordingly. you should be satistified when you get to tens of picoseconds of WNS, either positive or negative.

#### BigJJ

##### Newbie
In my case, start very big time period then reducing until the WNS is small negative.