What's the time delay between seq stat using variable?

Hi everybody!, consider this example,
PROCESS(clk)IS
VARIABLE a,b,c : STD_LOGIC;
BEGIN
IF RISING_EDGE(Clk) THEN
a:= '1';
b:= NOT(a);
c:= a OR b;
END IF;
END PROCESS;
The above statements should be executed in sequence,since the declaration type is a variable. How much time\clock cylces does it take for the successive statements to be executed one after another?...Is it the internal latency of the flipflop?.

zero

But it executes one after another. So there should be time difference,maybe the internal latency[/code]

But it executes one after another

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Not actually. the logic within clock synchronous sequential process is executed simultaneously at rising edge of clk. The logical result depends on statement order, but they are not executed one after another.

In the given example, no logic or flipflops are synthesized at all, cause the result is constant: a:='1', b:='0', c:='1'. Also internal signals with no output depending on it would be removed during HDL compiler optimization.

In the given example, no logic or flipflops are synthesized at all,

Click to expand...

If no logic gates are used in these statements then how are these variables declared or synthesized?...Though it is a constant, there must be some gates\flip0flops associated with this in order to store the value.....

The values of your variables are not driven by any input. Therefore they are constant values. When this is synthesized, the end result will be that a and c are wires connected to power, b is a wire connected to ground. This is the same as though you had simply written a := '1'; b := '0'; c := '1';

Continuing on, you are not actually driving any output with these variables. This entire process would be ignored by the compiler as if you had never written it.

Finally, variables are not stored anywhere (although you can use them to create storage). Processes and variables are an abstract way of describing the structure of a circuit, what you actually get from synthesis can depend entirely on the context that you use them in.

I'd go into more detail but it's 4 in the morning here. VHDL may look like any other programming language but it's a very very different world. IMO this can't be and isn't emphasized to beginners enough.

the end result will be that a and c are wires connected to power, b is a wire connected to ground. This is the same as though you had simply written a := '1'; b := '0'; c := '1'

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Hey "pongetti" thanks for your explanation. I'm unclear with one more fact. I've understood that only signals are wires connected to Vcc for '1' and Gnd for '0',whereas variables are for local storage. So I thought it may infer flipflops for storing '1's and '0'. Ok consider this eg.,
----------------
PROCESS(clk) IS
VARIABLE data_stack : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
data_stack := "10011010";
end process;
-----------------
Here,as per what you have said,does this variable "data_stack" be declared as series of 8-set wires(bus) connected to Vcc and Gnd as per it's assignment?...Ok if it's the actual case, then what happens when I drive this with some other source,for eg
-----------------------------------
PROCESS(clk,incr_val) IS
VARIABLE data_stack : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
IF RISING_EDGE(clk) THEN
data_stack := data_stack + incr_val;
end if;
end process;
----------------------------------
So in this approach how will the variable be treated?....Local storage or a bus type declaration?...Whether the synthesizer will infer flipflops for storage or just ignore?....Please illustrate....Thanks a thousand for your helping minds.

There is a big difference between those two circuits.

First of all, a variable does NOT equal local storage. A sequential process does NOT equal a sequential circuit. A process is an abstract way of describing a logic function. In traditional programming you are giving the computer a set series of instructions that get executed in sequential order one-by-one. With a VHDL process you are describing a logic function and the synthesizer will figure it all out and come up with a circuit that will give you the same END result. The sequential statements define the order of logic but in the end everything is executed at the same time.

Moving on, VHDL has a property where if there is a possible path in your process where you have not set the value of a variable or signal than it assumes that the variable/signal takes on it's previous value. In order to acheive this in hardware it must create a memory.

Ignoring the optimization talked about above (you are still not driving any output with either circuit), in your first example you would just get a constant "10011010" signal. There are no paths where the data_stack are not set.

In the second example you get a register for data_stack. There are paths here where your variable is not given a value. It doesn't look like it but there are. You have a check for rising_edge(clk), which means that you have not given data_stack a value to take on in the condition that rising_edge(clk) is false. So it infers a memory.

So you see, a variable does NOT equal storage, it's how you use it that infers storage.

If you add a second line so you have
data_stack := data_stack + incr_val;
data_stack := not (data_stack);

It will NOT set the value of the data_stack register as data_stack + incr_val, then set it again as not (data_stack). What it will do is roll out as if you had written
data_stack := not ( data_stack + incr_val );

If you want to learn more about the connection between what you write and what you get I'd personally recommend "RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability" by Pong P. Chu. I'm only at the intermediate level myself, more book knowledge than practice and this is really the only book I've ever read.

Great explanation....I got it....Thank you very much "Pongetti"....I just got a glance about that book, and I'm gonna order it today or as much earlier as possible though the price is steep at $99 at amazon...Anyway it's worth to learn....Similarly please provide support whenever we beginners stuck up...Thanks again....

$99 is very steep. The ebook seems to be all over the internet though. I don't like to go out of my way to encourage stealing so I'll make you look for it yourself but for $99 its nice to know you're getting what you want.

The downside to this book is that he all but ignores non-synthesizable code, so you're learning won't be totally complete afterwards but I found it was good at connecting coding to synthesis and making you think like you're creating a circuit rather than programming code.

but ignores non-synthesizable code

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Hello buddy,At the current technology level,the level of synthesizing is ok it seems...So I better prefer this book....Since you've said it covers right from the basic.I dont even know the meaning in gate-level for vhdl statements like IF-Else,Case etc, but I'm using it like software prog.So my project is inefficient. So I need this book right now...Since you've gone through this book,would you mind if I ask my doubts when it arises?...I guess the book itself shouldbe more self explanatory,but in rare case...
Regards

Hello Friend,

To assign 1 to 'a' after rising edge, it takes one data latching delay
To invert 'a' it takes one gate propagation delay
To find the OR logic it takes one logic finding delay.

Definitely it introduces some delay. To know the exact delay, go thro' the device datasheet. OK

If u need more details, contact me,

Regards,
N.Muralidhara
MSRS, CRL-Bangalore

Thanks dear pal, I will see to it...Ok could you help me get the right answer for this?....Consider that I would like to short the IO line of one device with the another through FPGA,then I write the code as,

Entity
.
Architecture
.
Begin
a <= b; -- I wanna move the input from b to a;
end

In this scenario,all I just do it to do a short. But I believe this short is untouched by the FPGA clock and it's a permanant logic. My doubt is that,wouldn't there be a short internal delay say,the latency of the buffer to latch the input to the output via the IOB?.....So the propagation time(pin-pin) + the buffer latching time adds the total timming whenever the state of the pin changes right?.....Is my statement correct?...So it's never equal to a physical short on a PCB,right?....Thanks

There is no latch time.

There are propagation delays for passing a signal through both an input and an output buffer.

You can ask the software for timing reports to see what your estimated delay is.