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Hi gck,
This time is genrally used in Flops, it is the amount of time taken to make a change at the Q from the moment when the clock edge is applied. This is very important in estimating the hold time.
Hey...
contamination delay is nothing but the minimum or the least amount of delay taken by the logic element...whereas critical path delay is the maximum delay taken by the logic element...of course it determines the Hold time in your design....
You need to understand that VALID inputs take time to appear as VALID outputs. This delay (or time) is nothing but the propagation delay.
But INVALID inputs take a finite time (or delay) too to appear as INVALID outputs. This is known as Contamination delay.
If you think it from transistor level point of view, think of the threshold voltage of the transistor. But if you are thinking from Digital point of view, think of the Noise Margin analysis.
Actually speaking you need the contamination delay only while designing circuits, else you can assume it zero in your timing analysis.
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