Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I think what the TS means is "How to make a simple processor pipelined?"
Anyways, if that is what you are asking then all you have to do is to split the simple processor code into further sub-modules which can operate independely and as a whole. Like the instruction fetching can be seperated from the execution unit, in that way you'll have a very basic pipeline but one that works.
thnx alot mohsin677.can i have some sort of documentation regarding this. some sort of description. i would need the pipelined version. of course the "helped" button would be pushed!!
Well code is very simple. i am sending you the diagram on which this code was made. Open the main.v file you will see '////' these line mark the boundary lines for each data memory as you will see in the diagram. Every component is in these lines for every memory unit .The instructions are stored in the instruction memory remember to give valid memory location in the instructions, for this take a look to data memory first. if you still have problems let me know i will send you the slides form which this was written this will explain you everything.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
