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Can Anybody Help me with this simple question?

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I will try to explain the first circuit from that you should be able to make out for the others...

A mos cannot conduct when Vgs<Vt... Since the capacitor can charge only when the MOS is coducting... the capacitor's voltage will be the maximum voltage for which the MOS can conduct... here in the first case for Vgs to be greater than 0.7V the capacitors maximum voltage can be 4.3V... thus the out put voltage is 4.3V...

Thus the answers will be

a)4.3V
b)4.3V
c)4.3V
d)3.3V
 

    ryusgnal

    ryusgnal

    Points: 2
    Helpful Answer Positive Rating
Correct Answers:
a) 4.3
b) 5.0
c) 4.3
d) 4.3
 

correct answers are
1) 4.3
2) 5
3) 4.3
4) 3.3

explanation requires a time consuming post which i'll send you later....btw you can consult good 0,poor 0, good 1 and poor 1 concept from book "cmos vlsi design by kamran eshraghian"...
 

Can u plz explain only how sencond o/p came to be 5 ....it should nt be 4.3

Added after 19 minutes:

Also for the last diagram (4) , the o/p at first level is 4.3 and next level it should be 4.3 -.7 , so 3.6 ?
Can u explain it ?
 

Vgs-Vt>Vds

and |Vgs| > |Vt| , Vgs should be more negative for pmos than Vt.
in nmos more positive.
when Vg=0 (second circuit),Vs is increasing (it makes Vgs more negative so the device is going towards ON side ).And when Vs reaches 5V (whole voltage at drain is mirrored at Source ),Vgs=-5V.But Vs cannot be taken to 0V level as (Vgs<Vt in pmos,it makes minimum voltage that can be get at source should be equal to Vt).

Added after 1 minutes:

this concept is defined in Kamran Eshraghian...
 

    ryusgnal

    ryusgnal

    Points: 2
    Helpful Answer Positive Rating
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