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Help needed in Asyncronous FIFO design

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satyakumar

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Hi all,
Im designing an dual port asyncronous FIFO with 16bit data width, writing at 25 Mhz and reading at 2.048 Mhz. My doubt is on how to overcome the jitter effect in 2.048 Mhz, and does this jitter effect the syncronization.

Thanks to all
 

When designing Asynch FIFO's care should be taken when calculating the FIFO depth. This depth is proportional to the burst read and write speeds from both sides. NExt comes the read and write pointer comparisions... to generate the empty flag, the write pointer has to be taken to the read clock side and synchronized with the read clock and then compared. The same goes for the full flag. This is mostly done using gray style pointers. Jitter can be over come by passing the respective signal through two D-FFs.

The best site for FIFO designs is the Sunburst Design site:

http://www.sunburst-design.com/papers/
 

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    satyakumar

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Hi vlsi_whiz,
Thanks for your reply, I got the basic idea in caculating fifo depth. If the write data burst is of 1kbytes for 1ms, and read burst is less. Then the maximum fifo depth would be not more than 1kbytes. If i keep the fifo depth double 2kbytes.
then any problem other than area increase.

Thanks
Satyakumar
 

the jitter effect in 2.048MHz has no so much effects on synchronization.




satyakumar said:
Hi all,
Im designing an dual port asyncronous FIFO with 16bit data width, writing at 25 Mhz and reading at 2.048 Mhz. My doubt is on how to overcome the jitter effect in 2.048 Mhz, and does this jitter effect the syncronization.

Thanks to all
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