help need for state machine outputs...

Hi

can anyone tell me do we need to clock the output assigned in a state machine before using it again in the state machine.

it is like a feedback. so do we need to clk it or not. i want to assign a flag in one state and then in some other state i need to check the status of this flag and decide the assignment of others signals..

thanks in advance.
tama

i have this problem too?help piz

Can you show a small example that clarifies your question? The answer may depend on your particular design.

In general, it's not necessary to insert flops into the feedback path of a synchronous state machine. However, an extra pipeline flop is sometimes helpful to break up a large combinatorial network, thereby allowing higher clock frequency. Such pipelining tends to increase design difficulty.

Hi Echo47

Thanks for ur reply.. i am trying to design a case statement(also trying to implement in a state machine) in which i am assigning some flags and checking some of these flags also to assign some signals.

eg...

process(x,y,z,u)
begin
flg1<= '0';
flg2 <= '0';
flg3 <= '0';
case (clk_st) is
when idle =>
......
when st1 =>
if(x = '1' and y = '1') then
flg1 <= '1';
else
flg1 <= '0';
end if;

when st2 =>
if(x = '1' and z = '1') then
flg2 <= '1';
else
flg2 <= '0';
end if;

when st3 =>
if(y = '1' and flg1 = '1') then ---- here in this state i want to check the status of
flg3 <= '1'; flg1 and as per that assign flg3.....
else
flg3 <= '0';
end if;
........

end case
end process...


as per the above case statment do i need to clk flg1 signals before checking it again.. I want to design a pipeline logic in which i will be using the flags as feedback also...


thanks in advance...
tama

I don't know what statemachine coding style ur using I suppose what you have
provided is statemachine output decoder code. You need to register the flags
in following way...

process(clk,rstn)
begin
if (rstn = '0') then
clk_st <= idle;
flg1 <= '0';
flg2 <= '0';
flg3 <= '0';
elsif (clk'event and clk = '1') then
clk_st <= clk_st_nx;
flg1 <= flg1_nx;
flg2 <= flg2_nx;
flg3 <= flg3_nx;
endif
end
-- next state decoder process
process(clk_st, x,y,z,u)
begin
case (clk_st) is
when idle =>
clk_st_nx <= st1;
.......
......
end case;
end
-- statemachine output decoder
process(clk_st, flg1, flg2, flg3, x, y, z, u)
begin
flg1_nx <= flg1;
flg2_nx <= flg2;
flg3_nx <= flg3;
case (clk_st) is
when idle =>
......
when st1 =>
if(x = '1' and y = '1') then
flg1_nx <= '1';
else
flg1_nx <= '0';
end if;

when st2 =>
if(x = '1' and z = '1') then
flg2_nx <= '1';
else
flg2_nx <= '0';
end if;

when st3 =>
if(y = '1' and flg1 = '1') then ---- here in this state i want to check the status of
flg3_nx <= '1'; flg1 and as per that assign flg3.....
else
flg3_nx <= '0';
end if;
........

end case
end process...


Hope this helps!

Hi Nand_gate
Thanks for ur reply... i got the idea about how to solve this problem...

thanks
tama...