How to know if the statement will be synthesized or not?

Hello all,

I'm using VHDL to model certain communication system, and i don't know which sentence of the VHDL syntax i use can be synthesized and which cannot, how can i be sure of them?

I need a tutorial about the FPGA flow starting from writing VHDL code down to burning to the FPGA chip... can anyone help me regarding that?

Thanks in advance,
Ahmad,

Which software and FPGAs are you using?

Refer to your synthesis tool documentation to see which HDL features it supports. For example, if you are using Xilinx ISE, see chapters "VHDL Language Support" and "HDL Coding Techniques" in your "XST User Guide".

hi ahmad,
you just have to follow certain rules
and avoid writing some codes
to ensure that ur design doesn't have latches (for instance,which isn't good in any synthesis)
these rules differ according to the software you are using
but there are general ones that u can follow
to avoid small mistakes
read any book for synthesis
there is: circuit synthesis with VHDL
also refer to "standard synthesis packages" IEEEStd1076.3-1997
"standard for VHDL register transfer level synthesis" IEEEStd1076.6-2004

Thank you echo47 and Salma

echo57,
I'm currently dowloading ISE webPACK 8.2i, i don't know what are you speeking about regarding your suggested readings? what is the XST user guide?

Salma,
Can you kindly upload your mentioned IEEE synthesis standards?

Thank you all..
Ahmad

XST is the name of the HDL synthesizer in Xilinx ISE. After you install ISE WebPACK, you should find the XST User Guide in the "Software Manuals" collection.

Maybe this will help you get started. It's my quick guide to creating and building a project in ISE Project Navigator:

1. Launch ISE Project Navigator (I'm using ISE Foundation 8.1i, other versions may work differently).
2. Click File -> New Project -> enter desired projectname/location -> HDL -> Next.
3. Choose your device type -> Next.
4. Click Next to skip the Create New Source dialog.
5. Click Add Source -> navigate to your Verilog/VHDL source file -> Open -> Next.
6. Click Finish -> Ok to accept all your project creation settings.
7. In the Processes tab, double-click Generate Programming File.
8. In a few seconds (or minutes or hours), it should synthesize (compile) your HDL, do place-and-route, and then create a configuration bitstream file that you can download to your device.
9. Optional: To see the routed chip layout, expand Implement Design in the Processes tab, then expand Place & Route, then double-click View/Edit Routed Design (FPGA Editor). To zoom-in, use Ctrl-Shift-click-drag. To zoom out press F6.
10. To download the bitstream to your FPGA, expand Generate Programming File and double-click Configure Device (iMPACT). When iMPACT starts, you may need to read its documentation because it supports many different download methods. Or you may get lucky using its default settings.

Thank you echo47 for your very detailed reply

But i have another small question, can the ISE webPACK synthesis the ASIC CMOS design from my VHDL code?!

Thank you very much..
Ahmad,

1. VHDL : programming by example by Douglas perry is one of the good book to know about VHDL language.
To be summerize :
This 'IF' statemet is a sequential statement, so it comes under a 'PROCESS'.
We can use this 'IF' statement for combinational as well as sequential logic.
If we use this 'IF' statement for combinational logic then it is compelsory to use 'ELSE' part of that 'IF' statement. But here you will get a prioritized combinational logic.
If we use this 'IF' statement for sequential logic then in that case we don't use 'ELSE' part. Then it will create registers/ flipflops/ latches.
If you want to learn more about, it is preferred to study the above book.

2. Xilinxproject navigator (ISE 8.1 or ISE 8.2) are the tools which can freely downloadable from www.xilinx.com site. There you can get the necessary information on 'How to download the program into fpga ?'.

ahmad_abdulghany said:

Thank you echo47 for your very detailed reply

But i have another small question, can the ISE webPACK synthesis the ASIC CMOS design from my VHDL code?!

Thank you very much..
Ahmad,

Click to expand...

ISE doesn't support ASIC
xilinx only deals with programmable logic
for ASIC, you should know the design flow of the fab
each one uses a set of different tools

for the standards, i don't have them cause i'm using resources partly extracted from them, they are available in the IEEE but i don't have the full access
you can use notes or slides
books would be great too
if u r working on a funded project you can get them for sure
if it's just ur own work then use resources online

In the erlier reply I was only discussed about 'IF' statement. But I am supposed to discuss about which statements are synthesizable.
'Time delays' can not be synthesizable. Because these time delays are depends upon which clock input we are using.
So 'WAIT' for some time delay statements are not synthesizable.
If you come to 'REPORT' statements, there is a message to be displayed when a certain condition occurs. There is no hardware logic for this type of text messages. So this statement also not synthesizable.
You have to practice much more on any synthesis tool to know more about synthesis.