Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How you know what is CDC

Thread starter choonlin
Start date Oct 7, 2006

Status: Not open for further replies.

Oct 7, 2006

#1

C

choonlin

Newbie level 4

CDc

Oct 7, 2006

#2

C

choonlle

Full Member level 2

Cross Clock Domain

Oct 7, 2006

#3

A

aji_vlsi

Advanced Member level 2

choonlin said:
CDc

By doing some google search

CDC - Clock Domain Crossing

Regards
Ajeetha, CVC
www.noveldv.com

Nov 20, 2006

#4

A

anovickis

Newbie level 5

cdc occurs when you have a signal that crosses from one clock domain to another clock domain

Status: Not open for further replies.

Similar threads

M
How to instantiate another vhd file inside testbench, where the testbench is used for opening files
- Started by metamisers
- Jan 6, 2024
- Replies: 6
PLD, SPLD, GAL, CPLD, FPGA Design
A
What is pixelclk in rgb2dvi digilent IP?
- Started by aminpix
- Dec 3, 2022
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
B
Port is not connected when using top module
- Started by Boris.b
- Jan 22, 2024
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design
H
[SOLVED] How do you use variable real numbers?
- Started by hobbskw
- May 13, 2022
- Replies: 2
PLD, SPLD, GAL, CPLD, FPGA Design
why in calculation on reg result is not know (XX)?
- Started by stackprogramer
- May 2, 2022
- Replies: 4
PLD, SPLD, GAL, CPLD, FPGA Design

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.

Accept Learn more…

Top