why in calculation on reg result is not know (XX)?

[stackprogramer]

When I want to calculate some operation I used a line of Verilog code:
With I used the below syntax and display it from $display I faced with: x

I:

temp_i_mult_result = temp_i_mult_result+data_i_buffer[j]*data_i_p_buffer[j];

II:
When I used this syntax I has no problem...It displays a valid number...

temp_i_mult_result = data_i_buffer[j]*data_i_p_buffer[j];

Why with the first line I faced unknown value in Verilog...
Thanks in advacne

 

[kaz1]

When I want to calculate some operation I used a line of Verilog code:
With I used the below syntax and display it from $display I faced with: x

I:

temp_i_mult_result = temp_i_mult_result+data_i_buffer[j]*data_i_p_buffer[j];

II:
When I used this syntax I has no problem...It displays a valid number...

temp_i_mult_result = data_i_buffer[j]*data_i_p_buffer[j];

Why with the first line I faced unknown value in Verilog...
Thanks in advacne

when simulating accumulator you need to define initial value. If it is unknown then all results are unknown. If it is hardware it may or may not start as zeros anyway.

 

[stackprogramer]

But before in initial block I initialize them with numbers.I even display and check them ...

 initial begin
          //Initial
k=0;
              for (k = 0; k < 96; k = k + 1)
              begin
                  data_i_p_buffer[k]=1;
                  data_q_p_buffer[k]=2;

              end
               for (k = 0; k < 128; k = k + 1)
              begin
                  data_i_buffer[k]=0;
                  data_q_buffer[k]=0;

              end
end

 

[kaz1]

But before in initial block I initialize them with numbers.I even display and check them ...

 initial begin
          //Initial
k=0;
              for (k = 0; k < 96; k = k + 1)
              begin
                  data_i_p_buffer[k]=1;
                  data_q_p_buffer[k]=2;

              end
               for (k = 0; k < 128; k = k + 1)
              begin
                  data_i_buffer[k]=0;
                  data_q_buffer[k]=0;

              end
end

your accumulator is "temp_i_mult_result", this needs be initialised.

 

[ads-ee]

You are using a blocking assignment for temp_i_mult_result?

If temp_i_mult_result is in an edge sensitive always block (i.e. implementing flip-flops) then you should be using a non-blocking assignment (<=). I've noticed in some previous code you posted that you always seem to use blocking assignments.

If this code is in a combinational always block then the initial value of temp_i_mult_result may or may not be indeterminate depending on the FPGA used even if you fix the simulation by adding temp_i_mult_result to an initial block.