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Vth variation of PMOS transistors

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jutek

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hello

is that possible the difference in Vth of pmos transistor is almost 300mV (-620mV and -916mV) !! for ss corner model and temperatures 125 and -40 adequatly ?

It's an AMS 0.35um. I think this change is too much so maybe the model includes errors?
 

Re: corners

No problem...
Commonly PMOS' Vth have a big-variation than NMOS in other fab.

I see that PMOS' 0.8~1.6(mV/'C) (= 100mV~200mV)
 

    J

    jutek

    Points: 2
    Helpful Answer Positive Rating
Re: corners

I think it's possible.

just for your reference: the IBM 0.18um that i'm currently, PMOS's vth variation is about 200mv.

you may use feedback circuit to compensate the process variation.


regards,
smart
 

    J

    jutek

    Points: 2
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Re: corners

always(at)smart said:
I think it's possible.

ou may use feedback circuit to compensate the process variation.

regards,
smart
Click to expand...

can you tell me what circuit you mean? i have to compensate this variation, cause in the worst case i have -920mV Vth with Vdd=1.3V !!!
 

Re: corners

Hi Jutek,

the process compesation technique is application depandent.

For an simple example: A voltage regulator which can regulate the stable output voltage at all corner.


you can probably post your circuit, without knowing it, it's hard help you.


regards,
smart
 

    J

    jutek

    Points: 2
    Helpful Answer Positive Rating
Re: corners

always(at)smart said:
the process compesation technique is application depandent.

For an simple example: A voltage regulator which can regulate the stable output voltage at all corner.

you can probably post your circuit, without knowing it, it's hard help you.

regards,
smart
Click to expand...

hi smart

it's just voltage regulator- LDO. It has two possible outputs 0.8V or 1.4V.
Output voltage is set by feedback resistors,i didn't draw the key which turns on or off resistor R1=75k. When vdd=1.3V only vout=0.8V is possible, when vdd is higher than 1.4V + dropout vout is 0.8V or 1.4V.

The main problem is pass device's size cause in this worst case i have -920mV threshold voltage with vdd=1.3V so it has to be W=120m wide!!!!
 

Re: corners

hi jutek,

ok, let's stick with the case when vdd=1.3v.

so in this case the vout = 0.8v, RL=8, so the driving current is 100mA,right? I think it just make sense to me, it need such a big size to current for so much current. Otherwise, if you decrease the size, the pass transistor will enter linear region.

I do not see it is a problem.


regards,
smart
 

Re: corners

always(at)smart said:
hi jutek,

ok, let's stick with the case when vdd=1.3v.

so in this case the vout = 0.8v, RL=8, so the driving current is 100mA,right? I think it just make sense to me, it need such a big size to current for so much current. Otherwise, if you decrease the size, the pass transistor will enter linear region.

I do not see it is a problem.

regards,
smart
Click to expand...

right iload is 100mA. it is a problem cause as you can see the circuit has huge variations in the corners

regards
 

Re: corners

Hi Jutek,

Pls label the signal.

One thing i can see from the waveform is that the phase margin is not well compensated yet.

Another thing is : why you call it corner? corner supposed to be simulated accoss all the PVT. or you meant something else?



regards,
smart
 

Re: corners

always(at)smart said:
Hi Jutek,

Pls label the signal.

One thing i can see from the waveform is that the phase margin is not well compensated yet.

Another thing is : why you call it corner? corner supposed to be simulated accoss all the PVT. or you meant something else?

regards,
smart
Click to expand...

yellow - typical 27
red - ss -40
beige(this one with yellow) ss +125
blue ff -40
green ff +125

right, phase margin is not compensated cause i've changed pass device's dimmensions and it presents big capacity now.

i call it corner cause lowest Vin=1.3V for LDO is the worst case so i don't use higher Vin.
I only change temperature and models=process.

Picture presents output voltage across process and temperature variations

regards
 

Re: corners

I think so that short-length MOSFET has a great influence on Vth Variation.
When VDD increasing, |Vth| be reduced by short-MOSFET effect.
Please check to simulate it by using 1um instead of 0.35um

and, plz show vin+, vin- signals.
 

    J

    jutek

    Points: 2
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Re: corners

ipierre said:
one question, Why dose Green signal show voltage drop?
Is it a supply voltage? forcing 1.3v at VDD?
Click to expand...

it was my mistake, now outputs looks much better

to Smart:

can you post this feedback circuit which can compensate process variations?
i could use smaller pass device then

thanks

regards
 

Re: corners

Jutek,

To me, the output variation is normal (with the corner), the overall variation in waveform shows only about 10mV (0.798~ 0.808v) across the process.


You may check if all the MOS in your design is in satuation or not? How much the loop gain variation across corner?


Regards,
Smart
 

Re: corners

hi
is it nessacary to guarantee all transistors in saturation in all process corners , specially VOLTAGE variation ,temp. ...? what about if the whole performance of the circuit within acceptable limit ..? i 've very small experience in that field
thanks
mahmoud;
 

corners

You should read AMS 0.35um technolog file. Vth is tested by foudry. If vth variation is written by AMS, it is correct.
 

Re: corners

Hi Jutek, I believe the last plot you shown is correct, and I guess the Green line is FF corner @125C, and the beige is SS corner @ 125C (I think SS 125C is the worst case under all conditions for LDO case), is that right? dear friend.
good luck.
 

Re: corners

smartdream said:
Hi Jutek, I believe the last plot you shown is correct, and I guess the Green line is FF corner @125C, and the beige is SS corner @ 125C (I think SS 125C is the worst case under all conditions for LDO case), is that right? dear friend.
good luck.
Click to expand...

hi

i don't know why, but the worst case is SS and -40C

What others corners i should check?
 

Re: corners

Comparison of twos as below.

Red ss -40 <-> Beige ss +125
Blue ff -40 <-> Green ff +125
Red ss -40 <-> Blue ff -40
Beige ss +125 <-> Green ff +125

Left's Vth is larger than Right's. so then Each vout levels are inversly regulated.
Analysis showed that it consisted of Vth.
(I guess the Pass tr. current isn't reliable when using Big W/L = 120mm/0.35um)

And, The worst case definition differs by design types. (Amp, Pass tr, resistance, capacitance etc...)
I think the worst case is Beige SS +125 in your LDO. (See ripple effect.)
 

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