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internal memory in a module

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samuel_raja_77

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1.For an fpga design what is the amount of the internal memory to be kept within in a module.
2.how to access this memory can it be like this
without clock
if(mem==23)
begin
end
or with respect to clock
 

which FPGA you are using ??
 

XILINX xc 2vp7 my doubt is whether we can have the inetrnal memory in our design
 

yes you can have.
 

how to access the internal memory can it be accessed like this in the state machine
if(mem==23)
begin
end
or with respect to clock
 

FPGA has different memory implementation.
1. Synchronous memory using block RAM.
2. Asynchronous memoru using CLB
3. Memory using FF's

The code which u have written array with index. Normally synthesis tool will not infer memory for such type of code. u have to write a code in the specified pattern defined by the synthesis tool.

the code u have written will infer flip flops with decoding logic implemented in CLB's
 
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