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RTL and Gate level simulation

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Hi all

could anybody tell me that what is the difference between RTL simulation and Gate level simulation.
cause behind the result mismaches between both.

Thanks
 

Gate level sim is usually check to ensure functionality is not lost during high level RTL to low level gates.
 

gate level simulation use real timing and simulation on RTL level intends only for functional check
 

RTL simulation is just Simulation of RTL code i.e Functionality
Gate level simulation is nothing but once design after synthesis , we will get gate laevl netlist this include statndard cell delays
 
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    LK@USA

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You can do Gate Sim for functional check or for timing check if you have back annotated timing information for the cells.
 

simply put, RTL simulation doesn't involve the propagation delay of the gates into consideration while verifying the functionality.

whereas, gate level simulation considers the delay of the gates during verification. The delays will change according to the library thats used for synthesis.
 

You can also cross check your STA constraints with gate Sims.
 

RTL Verfication is there is no Gates with delay addedBut in GATe level simulation Cella delays will be added
 

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