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ECO usually happens either in a very late stage of project, or a revision of the project. ECO stands for Engineering Change Order.
Suppose your design is synthesized, timing clear, and past the Place-and-Route stage. The netlist is ready and about to go out to get manufactured. But you find a bug in the design, or want to add some small feature to it. It is a waste of time to go back to pre-synthesis stage and redo all steps. That is why there are always some spare gates kept on the chip layout. If you decide to debug something or add some logic, these spare gates are used (on the already P&R netlist) to add or modify any piece of logic. These spare gates are already placed, hence only routing and re-verification of timing needs to be done.
NanDigits Design Automation provides netlist ECO tool, GOF, Gates On the Fly. It's free for none-commercial and evaluation purpose. Check it out https://www.nandigits.com/products.htm
when something went wrong you don't resynthesis and instead you use the spare cells to correct the circuit to what you want. Sometime it is difficult to do it because the circuit complexity especially happens in FSM.
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