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ATPG gate level simulation w/ annotated timing

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cheelgo

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Currently I encounter big problem for kind of transition pattern simulation w/ sdf.
use 1000 patterns.
In MAX condition, pattern simulation is clean w/o mismatches.
but in MIN condition, pattern simulation encounter huge number of mismatches, but limit to like 14 pattern out of 1000 patterns failed. for ex. simulation value is 1, but expected value is 0.

currently I don't know where begin to do analysis.
many thanks for your help.
best regards
Cheelgo
 

From your describption, it is more likely a problem on timing. Can you figure out which FF make this mismatch? Then you can dump the waveform of the scan fail chain when you simulate with the error pattern. In my experiment, this is may be clock skew problem between different clock tree which are generated seperately.

Sincerely,
Jarod
 

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    cheelgo

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Hi Jarod,
thanks for your answer.
I have figure out some FFs faile in one test patterns. but I don't know how to dump the waveform of the scan fail chain. could you give me some reference or some instruction for doing this kind of dump.
Meanwhile, I also check that these Mismatches mostly are hard mismatches ( 1 vs. 0).
if we can confirm this is due to clock skew, what we can do for get clean/stable test pattern for test engineer?

Best Regards
Cheelgo
 

Hi Cheelgo,
I had only use the syntest's tool to generate the test pattern. In the test pattern generation, it will also output the information that contain all FFs belonged to each chain in presentation of hierachical instance name. By writing some scripts to extract this information and write the statements that dump wave of each FF you want. In simulation,
you only need to include the file generated above.

Sincerely,
Jarod
 

Hi Jarod,
I know how to do run simulation interactive mode to observe the FF's signal. -- this FFs cause mismatches in simultion.
what's mean by dump, this is better for debug or for batch run?
till now I know the ffs related to scan chain and failing ffs for failing pattern, but don't do dump.
thanks
Cheelgo
 

Hi Cheelgo,
Could you tell me what ATPG tool you use, and what tool you use to run simulation. I use Syntest Turboscan to generate the test pattern, and then use ncverilog to run these test pattern with fsdbDumpvars() statement.

Sincerely,
Jarod
 

Hi Jarod,
I use FastScan to generate pattern and use Mentor Modelsim to simulate pattern.
after dump, which is the next step?

thanks
Cheelgo
 

Hi cheelgo,
The next step is just like normal debuging with simulation. You can view the input/output signals of the fail FF and its related FF, especially the clock pin.

Sincerely,
Jarod
 

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    cheelgo

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Hi Cheelgo,
I think you design has hold timing violations about DFT scan chain.Are you sure in STA process,there is no setup/hold timing violations(MAX and MIN) in you design?
 

Hi flyingjk,
my DFT scan chain test pass MIN/MAX without mismatch.
thank you.
Cheelgo
 

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