Parastic capcitance in CMOS

capcitance -1.46a

Hi,

The main problem of IC analog design is the rising of parastic capcitance of CMOS,
and that is mainl in high speed application. This capacitance come from different transistor compnents and layers. What is most parameters that is effecting that capacitance and how they modeled in IC. Is there any routing procedure to decrease it. Any issue related.
tahnks

After layout, use some extraction tools like Arcadia to extract your circuit and simulate again using the extracted circuit.

Just my own experience, trace length and large size are the main cause of parasitics.

Hi,

As dumbfrog said you should in any case simulate post layout. Also you can extract your layout while you are doing it, it's the best way to correct or optimize it.
In high speed layout you usually use top metal for the main paths but you should take care of spacing with this metal because of the thickness. The fringing capacitance is huge. Always use 3 or 4 times the min spacing.
Shiekd the clock. Be carefull to the extra cap to ground. You should fix your clock buffer.
Shield noisy net.
Shield analog routing at the toplevel.
Use mim capacitor to run your RF net.
I should also say that simultaneous TOP and CELL floorplan is the basis to optimize the length of your critical routing.
Avoid cross between GATE and DRAIN.
diagonal routing to optimize length.
hexagonal pad.
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