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[SOLVED] Tried simulating DDR4 Interface simulation using system verilog in ModelSim PE Student edition and my package file shows some error

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Prethiga

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C:
'ifndef DEFS_DONE
   'define DEFS_DONE

package ddr_pkg;

   //implemenented for 2gb so row_addr is 14 bit
   parameter CHIP_ID  = 3'b101;
   parameter BG_WIDTH = 2;
   parameter BA_WIDTH = 2;
   parameter RA_WIDTH = 15;
   parameter CA_WIDTH = 10;
   parameter TA_WIDTH = BG_WIDTH + BA_WIDTH + RA_WIDTH + CA_WIDTH;
   parameter ADDR_WIDTH = 32;    //physical addr
   parameter NUMBER_BANK= 16;    //number banks in dimm
   parameter MRS_WIDTH  = 19;
 
 
   parameter DATA_WIDTH = 8;
   parameter FALSE    = 1'b0;
   parameter TRUE     = 1'b1;
   parameter HALF_PERIOD  = 1.25/2;
   parameter QUARTER_PERIOD = 1.25/4;
 
   parameter READ     = 2'b01;
   parameter WRITE    = 2'b10;
 
   //timing parameter
 
   parameter nCK      = 1.25;
   parameter tRTP     = int'(7.5/nCK);
   parameter tWTR     = int'(7.5/nCK);
   parameter tWR      = int'(15/nCK);
   parameter tRP      = int'(12.5/nCK);
   parameter ACT_DELAY = int'(7.5/nCK);         //act to act cmds latency
   parameter tRCD      = int'(12.5/nCK);
   parameter CAS_DELAY = int'(12.5/nCK);        //act to cas cmd latency


   //timming parameter for reset
   //parameter tCKE_L   = 500000/nCK;
   parameter tCKE_L   = int'(500/nCK);
   parameter tXPR     = 5;
   parameter tMRD     = 8;
   parameter tMOD     = 24;
   parameter tZQ      = 4096;
   parameter tIS      = 10;
   parameter tRAS     = int'(25/nCK);            //act to precharge latency
   parameter tREF     = int'(7800/nCK);          //7.8us
   parameter tRC      = int'(47.5/nCK);                //refresh to act
 
 
   //temporary define enum for commands
   typedef enum {MRS, REF, PRE, ACT, CAS_R,CAS_W, NOP, DES,ZQCL} cmd_name;
 
   //typedef for states in DDR CONTROLLER
   typedef enum {CTRL_IDLE, CTRL_INIT, CTRL_RW, CTRL_UPDATE,
                 CTRL_WAIT, CTRL_REFRESH, CTRL_ACT}
                ctrl_fsm_type;

   //typedef for states in BURST_ACT
   typedef enum {ACT_IDLE, ACT_WAIT_STATE, ACT_CMD, ACT_CAS, ACT_ONE_DELAY,
                 ACT_TWO_DELAY,PRE_WAIT_DATA, PRE_WAIT_STATE,
                 PRE_CMD, PRE_IDLE} act_fsm_type;
 
   //typedef for states in BURST_CAS
   typedef enum {CAS_IDLE, CAS_WAIT_STATE, CAS_CMD,
                 CAS_WAIT_DATA, CAS_WAIT_EXTRA} cas_fsm_type;
   //typedef for states in fsm in BURST_RW
   typedef enum {RW_IDLE, RW_WAIT_STATE, RW_DATA} rw_fsm_type;
 
 
    //typedef for write data (data-out)   
   typedef logic [8*DATA_WIDTH -1:0]    data_type;

   //typedef  for physical address
   typedef logic [ADDR_WIDTH -1:0] addr_type;
 
   //typedef  for physical address
   typedef logic [TA_WIDTH -1:0] dimm_addr_type;
 
   //typedef for MRS register from stimulus
   typedef logic [MRS_WIDTH -1:0] mode_register_type;

 
   typedef struct packed { logic [BG_WIDTH -1:0] bg_addr;
                           logic [BA_WIDTH -1:0] ba_addr;
                           logic [RA_WIDTH -1:0] row_addr;
                           logic [CA_WIDTH -1:0] col_addr;
                         } mem_addr_type;
 
   //typedef for data in include address, data, read or write request
   typedef struct packed { addr_type physical_addr;
                           data_type data_wr;
                           logic [1:0] rw;
                          } input_data_type;
                         
 
   //typedef for act data type include ba, bg, and row address
   //typedef mem_addr_type act_data_type;
                        
   //typedef for cas data type include ba, bg, and row address
   typedef struct packed {mem_addr_type addr;
                          logic [1:0]   rw;
                          }cas_data_type;
                        
                        
   //typedef for rw data type include ba, bg, and row address
   typedef struct packed {data_type data_wr;
                          logic [1:0] rw;
                          int burst_length;
                          int preamble;
                          }rw_data_type;
                           
   //define type for control commands, and MRS registers
   typedef struct packed { cmd_name cmd;
                           cas_data_type cmd_data;
                           } command_type;

                         
endpackage    
import ddr_pkg::*;
'endif


The error shown is

** Error: (vlog-13069) C:\Users\..\DDR\ddr_package.pkg(5): near "ddr_pkg": syntax error, unexpected IDENTIFIER.

** Error: C:\Users\..\DDR\ddr_package.pkg(5): (vlog-13205) Syntax error found in the scope following 'package'.


Is there a missing '::'?
 
Last edited by a moderator:

compile it using -sv on the vlog command line.
The file is a Systemverilog file.
--- Updated ---

That is why you have unexpected identifier near ddr_pkg the identifier is the systemverilog keyword "package"
 
Thank you very much. I tried it and it got fixed but while trying to simulate I am getting this error I am not sure what file to edit to fix it
2020-10-01.png
 

It means that the file that has the ddr_pkg was modified at some point after the other files like test_sv_unit and top were compiled. You need to ensure all files have been compiled before launching vsim.

If you are compiling with a modelsim project file then you need to make sure you add all the files including the ddr_pkg file into the project, otherwise it won't be compiled.
 

    Prethiga

    Points: 2
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