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Design a 2^8 row decoder using less transistor

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invincibleuiu

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hello,
I want to design DDR RAM.anybody can suggest me how can i design a row decoder and column decoder using less transistors.here i give a picture of a row decoder.but i can not understand how i sketch the row decoder from this picture. 403521ad.2.gif

thanks
Shayadul Alam
 

Can you make use of a tri state device to store. An 8 bit CMOS or TTL can do. If you need to cascade this chip, then you can increase your address line. write and read control will be implemented as well. Good luck.
 
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