Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Design a 2^8 row decoder using less transistor

Status
Not open for further replies.

invincibleuiu

Newbie level 4
Joined
Aug 12, 2015
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
47
hello,
I want to design DDR RAM.anybody can suggest me how can i design a row decoder and column decoder using less transistors.here i give a picture of a row decoder.but i can not understand how i sketch the row decoder from this picture. 403521ad.2.gif

thanks
Shayadul Alam
 

ahmed-agt

Member level 5
Joined
Nov 12, 2012
Messages
92
Helped
8
Reputation
16
Reaction score
8
Trophy points
1,288
Location
Nigeria
Activity points
1,818
Can you make use of a tri state device to store. An 8 bit CMOS or TTL can do. If you need to cascade this chip, then you can increase your address line. write and read control will be implemented as well. Good luck.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top