zhangpengyu
Full Member level 3
help for vcs
Hi
I want to partiton a chip-level design(verilog + pli) to several parts(6 parts for exapmle),and use vcs to simulate each part(6 vcs processes run paralleling),then
I could distribute these processes to different cpus(6 cpus SMP for example) to
accelerate simulation.
I think it's distributed parallel simulation.But I don't know how these vcs processes communicate each other.
Is this possible for me to do this?Does vcs support this? How could these processes communicate each other?
Help please!!
zhpy
Hi
I want to partiton a chip-level design(verilog + pli) to several parts(6 parts for exapmle),and use vcs to simulate each part(6 vcs processes run paralleling),then
I could distribute these processes to different cpus(6 cpus SMP for example) to
accelerate simulation.
I think it's distributed parallel simulation.But I don't know how these vcs processes communicate each other.
Is this possible for me to do this?Does vcs support this? How could these processes communicate each other?
Help please!!
zhpy