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question about initial statement

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beowulf

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How is the verilog 'initial' statement interpreted by Synopsys. I have heard different opinions, some say it is not synthesizable some say it is.
Please let me know.

Also where would I find a list of statements (Verilog) that are synthesizable and how they are interpreted by Synopsys.

Thanks,
Beowulf
 

If I not mistaken, I dont use initial for RTL code since it is not synthesizable.

I only use it inside my testbenches for simulation and in behavioral code. 'initial' statement is use to initialize ur input of a design in simulation.

Correct me if I'm wrong.

-no_mad
 

when I write RTL code , not use "initial"
"initial" only use to simulation and debug
 

my exoerience...using

Initial statement in Verilog is Purely...for behavioral modeling...and not for RTL....

thnx
 

Initial can't synthesis, if you want to improve you rtl coding style ,you should first read RMM,
which is very good for newbie.
 

stormwolf said:
Initial can't synthesis, if you want to improve you rtl coding style ,you should first read RMM,
which is very good for newbie.
Click to expand...

What is the RMM, where can I find it?

Any other document which gives a list of verilog statements which are synthesizable will be of great help

Thanks,
B
 

RMM is the Reuse Methodology Manual..

Its available in the Ebooks section.

hxxp://

You may want to check out the Verilog Synthesis Primer too..

jelydonut
 

Initial Statement is ignored by Synopsys (any synthesis tool).
You can use initial statement only in testbench/testcase etc, not in RTL.
Try some elementary books on Verilog or refer to Solvnet

- A
 

Thank you all for the replies and the reference to RMM.

Can anybody help me access Solvenet, there is loads of info there and I can create my own account, but i do not have access to the Synopsys license.

Thanks
Beowulf
 

initial can not synthesized ,u better use assign and always for coding .then u can design things with always and assign ..
 

shashi_reddy21 said:
initial can not synthesized ,u better use assign and always for coding .then u can design things with always and assign ..
Click to expand...

Thanks Sashi,
Any example of how to use assign and always for replacing 'initial' eg:

if I am using a clock generator and i say

initial
clk = 1'b0;

how would i do this within an always with an assign, (can I use an assign statement within always?)

this is how i think it might be done but I'm not sure

always @ (say_reset)
begin
assign clk <= 1'b0;
"
"
end

but is this valid? all comments will be helpful
 

Hi Beofulf,

You cannot infer a reliable clock generation circuit by writing RTL. This is usually using crystals and PLL's in real designs.
 

You can't use assign statement inside the "always" block.

"assign" is for combonational logic design.
"always" statement are always available for execution. Every time the input in the senstivity list change.


For more details, I think u can read from any verilog books or use any search engines to find it.
 

these are some tips from my side while u writing synthesizable codes


i#itial Used only in test benches.


#Events make more sense for syncing test bench components

#Real data type not supported.


#Time data type not supported


#orce and release of data types not supported


#assign and deassign of reg data types is not supported. But assign on wire data type is supported

#ork join Use nonblocking assignments to get same effect.


#nly gate level primitives are supported

# UDP and tables are not supported.
 

Thanks all for the reply,
1. Does synopsys have a list of verilog constructs that can be synthesized ?

2. Can anybody help me access Solvnet site? I do not have the license # required to register.

B
 

clk is not synthesizable and we are not going to use it in the synthesis,clk is given at chip level by pll using oscillator,so u dont worry abt clk ,just us it simualtion to check the functionality
 

beowulf said:
Thanks all for the reply,
1. Does synopsys have a list of verilog constructs that can be synthesized ?

2. Can anybody help me access Solvnet site? I do not have the license # required to register.

B
Click to expand...
Here is the synthesisable handbook
 

    B

    beowulf

    Points: 2
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beowulf said:
How is the verilog 'initial' statement interpreted by Synopsys. I have heard different opinions, some say it is not synthesizable some say it is.
Please let me know.

Also where would I find a list of statements (Verilog) that are synthesizable and how they are interpreted by Synopsys.

Thanks,
Beowulf
Click to expand...
this is the book for the synthesis and simulation construct in verilog
 

initial is not synthesised and this is been used in the test bench
and it is executed only once

and mainly used to initialise the values.

if i am wrong please correct me

thank you.


beowulf said:
How is the verilog 'initial' statement interpreted by Synopsys. I have heard different opinions, some say it is not synthesizable some say it is.
Please let me know.

Also where would I find a list of statements (Verilog) that are synthesizable and how they are interpreted by Synopsys.

Thanks,
Beowulf
Click to expand...
 

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