eastwinter1
Newbie level 2
Hi everyone,
I want to design a module to implement QR decomposition of a 4*4 matrix on FPGA, I have already write C code in a FSM-like fashion for the algorithm, and it works well.
Then I try to convert it to verilog using FSM(Finite State Machine), since division cannot be avoided in QR decomposition, I decided to use the Divider IP core in ISE, typically the latency of the divider is about 20-30 clock period.
When I use C ,I use division in this state, I get the result immediately,and can use the result in the next stage.But in verilog, since the latency of the divider is 20 clock period(for example), so how do I write the FSM ? Do I need to write 19 states that do nothing ?
New in digital design, hope someone helps.
I want to design a module to implement QR decomposition of a 4*4 matrix on FPGA, I have already write C code in a FSM-like fashion for the algorithm, and it works well.
Then I try to convert it to verilog using FSM(Finite State Machine), since division cannot be avoided in QR decomposition, I decided to use the Divider IP core in ISE, typically the latency of the divider is about 20-30 clock period.
When I use C ,I use division in this state, I get the result immediately,and can use the result in the next stage.But in verilog, since the latency of the divider is 20 clock period(for example), so how do I write the FSM ? Do I need to write 19 states that do nothing ?
New in digital design, hope someone helps.
