the use of divider in FSM

[eastwinter1]

Hi everyone,
I want to design a module to implement QR decomposition of a 4*4 matrix on FPGA, I have already write C code in a FSM-like fashion for the algorithm, and it works well.
Then I try to convert it to verilog using FSM(Finite State Machine), since division cannot be avoided in QR decomposition, I decided to use the Divider IP core in ISE, typically the latency of the divider is about 20-30 clock period.
When I use C ,I use division in this state, I get the result immediately,and can use the result in the next stage.But in verilog, since the latency of the divider is 20 clock period(for example), so how do I write the FSM ? Do I need to write 19 states that do nothing ?

New in digital design, hope someone helps.

 

[ads-ee]

If the core has a fixed latency, which for a divider algorithm should be the case (clock cycles same as bit width), then you should just wait in the "divide" state for the required number of clock cycles until the divide is finished. If the divider IP has a signal to indicate a valid output for the division use that to transition out of the "divide" state, otherwise spin in the divide state.

Regards

 

[eastwinter1]

OK，I see. Thank you.