Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How can submodule constraints transferred to uplevel

Status
Not open for further replies.
W

wkong_zhu

Full Member level 3
Joined
Nov 13, 2004
Messages
174
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,296
Activity points
1,293
propagate_constraints

I use bottom-up synthesis method, I set timing constraints on submoduleA, and compile it, then set_dont_touch it, After that, I read the top module file, which instantiated the submoduleA, but I find that, the top module has no timing constraints now, I have to re define the timing constraints for the top module.

The top module timing constraints is almost the same the submoduleA, the clocks are defined in the submoduleA's internal module Pins. So the re-definition of timing constraints of top module seems to be superfluous and tidious.

How can DC directly transfer submodule timing constraints to uplevel module??
 

dc disable_timing

hi, refre to DC manual, there are detailed info about the hierarchy synthesis method
 

module timing constraints

If you have hierarchical designs and compile the subdesigns, then
move up to the higher-level blocks (bottom-up compilation), you can
propagate clocks, timing exceptions, and disabled timing arcs from
lower-level .db files to the current design, using the
propagate_constraints command.
The syntax is
propagate_constraints
[-design design_list]
[-clocks] [-false_path]
[-multicycle_path]
[-max_delay] [-min_delay]
[-disable_timing] [-gate_clock -all]
[-ignore_through_port_exceptions]
[-ignore_from_or_to_port_exceptions]
[-verbose] [-dont_apply]
[-output file_name]
 

I think , the better way is write a top-level constarint, using budgte to generate submodule constraint, then bottom-up.
 
  • Like
Reactions: pchan

    P

    pchan

    Points: 2
    Helpful Answer Positive Rating
Please tell me more details of budget to generate submodule constraints. I'm interested in it. how can i find the the detail document.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top