Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Interview Question for ASIC Design

Status
Not open for further replies.
N

nandithaa_m

Junior Member level 3
Joined
Jan 2, 2008
Messages
27
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
USA
Activity points
1,473
Hi Guys,

I am preparing for an interview and can you provide me an answer for the following question ?

Why do designers avoid a clock with 0 rise time ?
 

I hope I understood your question correctly; I've got to say: because it's impossible to build a clock with rise time = 0.
So we have to consider the rise time effect on our design.
 

Hello,
Rise time means 0 to 1 transition, now question is how 0 to 1 transition occurs,for occurring,0 to 1 transition,these should pass through some logic...if is pass through some logic,thn it is not possible to do it with 0ns delay...so we need to consider rise time..and same for fall time..
 
To reduce also the clock feedthrough effect=> reduce errors
 

designers don't avoid it... zero transition is not possible to acheive so designers account for it.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top