Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
During the Fabrication Process the large amount of charge is induced
in plasma etching, ion implantation and in other processes.
If a large interconnect (Poly or other Conducting material) is
connected to the Gate of a MOSFET, then this larger conducting
material will act as Antenna and will receive the induced charge of
the Fabrication Process.
The charge due to these extra carriers might be too much for the thin
gate to handle it, and it may also damage the thin oxide layer.
So, Antenna effect may result in breakdown of Gate Oxide or degrade
the I-V Characteristics.
To avoid the antenna effect we need to
1) avoid large Interconnect Area to Gate of a MOSFET by breaking down metal 1 to metal and metal 2 (see fig)
2) we can also use the diode placed near the MOSFET as in fig
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
