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[SOLVED] Design Compiler - Connect all ports

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meldron1X

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Hello,

I'm using Synopsys Design Compiler for synthesis. Does anybody know how I can connect all ports of my gates when I'm writing out my netlist?
E.g.:
DC writes as netlist (verilog):

'DFF DF1 ( .D(n1), .C(clk), .RN(reset_n), .Q(n2));'

ignoring port QN which is not used.
But, I would like to have this port also in my final netlist, like this:

DFF DF1 ( .D(n1), .C(clk), .RN(reset_n), .Q(n2), .QN(dummy) );

Thank you for help/hints
 

This usually results in creating a node called "dummy" and driving it with every unused flip-flop output in your module.

Try leaving it with a port name and no signal name
 

Hi jt_eaton,

thank you for your reply and sorry for my late answer.
My question is, how can I automate (by the DC) the inclusion of this node 'dummy'? Currently, DC completely ignores every unconcerned port and doesn't print it in the netlist.

Cheers
 

set verilogout_show_unconnected_pins true

Try this option before you write out netlist. It should work.
 
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