Will the following "LSB first shift right register" synthesize correctly ?

shaiko · Aug 22, 2012

"vector" is a 32 bit wide unsigned input to an entity.
"width_of_vector" is an 8 bit wide unsigned input to the same entity. "width_of_vector" is responsible for setting the dynamic width of "vector".

will the following "LSB first shift right register" synthesize correctly ?

Code:

process ( CLK , RST ) 
begin 
  if RST = '1' then
     data <= ( others => '0' )		
  elsif shift = '1' then
     data ( to_integer ( width_of_vector ) - 1 downto 0 ) <= data & ( data ( to_integer ( width_of_vector ) - 1 downto 1 ) ) ;					   		  
  end if ;
end process ;

-- "width_of_vector" isn't a constant! It's an entity input!

dftrtl · Aug 22, 2012

Re: VHDL synthesis question

Yes Why do you think it will not.

shaiko · Aug 22, 2012

Re: VHDL synthesis question

I just tried it with Quartus - it fails!
The error message is as follows :
"left bound of range must be a constant"

guitarguy12387 · Aug 22, 2012

Re: VHDL synthesis question

shaiko said:
I just tried it with Quartus - it fails!
The error message is as follows :
"left bound of range must be a constant"

width_of_vector cannot be a signal. Make it a generic if you want to pass its value during instantiation.

TrickyDicky · Aug 22, 2012

Re: VHDL synthesis question

first of all, I assume this isnt the actual code you're working on.
data(n-1 downto 0) <= data & data(n-1 downto 0);

do you see the problem? (basically, you're trying to fit an array almost twice as big into itself). So I assume you meant ip & data(n1 downto 0);

This is more a VHDL thing. I can see you want to set the enables true on only a selected number of regusters in the shift register, with the input a mux selected between ip and the previous register. but like the error says, slicing an array must be constant. (why do it this way round, why not have the ip always connect to 0 and have the output just mux off which bit it needs?)

Use a for loop, something like:

Code:

for i in 1 to data'length-1 loop
  if width_of_vector = i then
    data(i) <= ip;
  else
    data(i) <= data(i-1);
  end if;
end loop;

shaiko · Aug 22, 2012

Re: VHDL synthesis question

do you see the problem? (basically, you're trying to fit an array almost twice as big into itself). So I assume you meant ip & data(n1 downto 0);

Sorry, TrickyDicky - what I meant is :

Code:

data ( to_integer ( width_of_vector ) - 1 downto 0 ) <= input  & ( data ( to_integer ( width_of_vector ) - 1 downto 1 ) ) ;

Your proposal isn't appropriate for my application.
As I said, I need a shift register that can "adapt" after synthesis...
For example, think of a UART with a variable word width that can be changed between transmissions according to the control signal "width_of_vector".

std_match · Aug 23, 2012

Re: VHDL synthesis question

How would you do it if you had to manually draw a schematic?
What you ask for is complicated. It can be described by a schematic and in VHDL but the probability is high that there is a better solution.

You should describe the input and the final result, then we can help to find the best solution.

Do you really need some bits to be unchanged while the other bits are shifted?
Do you really need to shift at all? If you are only interested in the final result, maybe the best solution is to store each bit directly in it's final position.

If I had to follow your code strictly, I would probably decode the "width_of_vector" to a one-hot signal that indicates where in the shift register
the border is between "shift" and "don't shift". The shift register would be a one-bit slice in a generate loop. Each slice propagates the shift/don't shift to the next slice, but first gate it with the one-hot signal.

shaiko · Aug 23, 2012

Re: VHDL synthesis question

Do you really need to shift at all? If you are only interested in the final result, maybe the best solution is to store each bit directly in it's final position.

std_match,
Indeed, I don't need to shift. I'm only interested in the end result.
That's exactly how I decided to workaround the problem.

FvM · Aug 23, 2012

Re: VHDL synthesis question

Your proposal isn't appropriate for my application.
As I said, I need a shift register that can "adapt" after synthesis...
For example, think of a UART with a variable word width that can be changed between transmissions according to the control signal "width_of_vector".

The suggested iteration loop is the appropriate way to achieve what you want. Why do you think that it can't adapt the length of a shift register? It can pretty well.

shaiko · Aug 23, 2012

Re: VHDL synthesis question

FvM, TrickyDicky

Can you please explain what this block of code does ?

Code:

for i in 1 to data'length-1 loop
  if width_of_vector = i then
    data(i) <= ip;
  else
    data(i) <= data(i-1);
  end if;
end loop;

TrickyDicky · Aug 23, 2012

Re: VHDL synthesis question

Exactly what you tried to do in your origional post.

- - - Updated - - -

In full context:

Code:

process ( CLK , RST )           
begin                           
  if RST = '1' then               
    data <= ( others => '0' )       
  if rising_edge(clk) then
    elsif shift = '1' then          
      
      for i in 1 to data'length-1 loop
        if width_of_vector = i then       
          data(i) <= ip;                  
        else                            
          data(i) <= data(i-1);           
        end if;                         
      end loop;                       
      
    end if ;                        
  end if;
end process ;

shaiko · Aug 23, 2012

Re: VHDL synthesis question

TrickyDicky,

Suppose "data" is defined as unsigned ( 2 downto 0 ) and it's "000" after reset.
Then, the value at the "width_of_vector" input is set "10" (integer 2).
This means that we intend to shift twice.
Now, lets assume that we move "11" to the register ( 2 shifts with logic '1' at the input each time).

It seems that with your code the value of "data" after the dual shift will be "110" - But I need it to be "011"......................

FvM · Aug 23, 2012

Re: VHDL synthesis question

It seems that with your code the value of "data" after the dual shift will be "110" - But I need it to be "011"......................

Then you'll want to change your original code to a left shift. But it's a right shift now, same as the suggested one.

Code:

data ( to_integer ( width_of_vector ) - 1 downto 0 ) <= input  & ( data ( to_integer ( width_of_vector ) - 1 downto 1 ) ) ;

Seems like you mean

Code:

data ( to_integer ( width_of_vector ) - 1 downto 0 ) <=  (data ( to_integer ( width_of_vector ) - 2 downto 0 ) )&  input ;

shaiko · Aug 23, 2012

Re: VHDL synthesis question

So, the only change will be + instead of - ?

Code:

process ( CLK , RST )           
begin                           
  if RST = '1' then               
    data <= ( others => '0' )       
  if rising_edge(clk) then
    elsif shift = '1' then          
      
      for i in 1 to data'length-1 loop
        if width_of_vector = i then       
          data(i) <= ip;                  
        else                            
          data(i) <= data(i+1);           
        end if;                         
      end loop;                       
      
    end if ;                        
  end if;
end process ;

FvM · Aug 23, 2012

Re: VHDL synthesis question

So, the only change will be + instead of - ?

Neither correct. I just noticed that the suggest code from post #5 combines a left shift of the register content with concatenation at the MSB, which is neither regular left nor right shift.

A left shift restricted to width_of_vector bits should look like this

Code:

process ( CLK , RST )           
begin                           
  if RST = '1' then               
    data <= ( others => '0' )       
  if rising_edge(clk) then
    if shift = '1' then          
      data(0) <= ip;
      for i in data'length-1 downto 1 loop
        if i < width_of_vector then       
          data(i) <= data(i-1);           
        end if;                         
      end loop;                       
    end if ;                        
  end if;
end process ;

shaiko · Aug 23, 2012

Re: VHDL synthesis question

Wouldn't it be better to use an incrementing bit counter and simply write ?

Code:

data ( bit_counter ) <= ip ; -- bit_counter counts each shift

FvM · Aug 23, 2012

Re: VHDL synthesis question

If you want a shift register, why?

shaiko · Aug 23, 2012

Re: VHDL synthesis question

BTW,
As you said this code is for

left shift restricted to "width_of_vector"

meaning, MSB is sent first...
How will the code look if we still want the "width_of_vector" restriction with shift right ( LSB sent first ) ?

FvM · Aug 24, 2012

Re: VHDL synthesis question

How will the code look if we still want the "width_of_vector" restriction with shift right ( LSB sent first ) ?

Very similar to your code from post #14, I think

Code:

process ( CLK , RST )           
begin                           
  if RST = '1' then               
    data <= ( others => '0' )       
  if rising_edge(clk) then
    if shift = '1' then          
      
      for i in 0 to data'length-1 loop
        if i = width_of_vector then       
          data(i) <= ip;                  
        elsif i < width_of_vector then             
          data(i) <= data(i+1);           
        end if;                         
      end loop;                       
      
    end if ;                        
  end if;
end process ;

shaiko · Aug 24, 2012

Re: VHDL synthesis question

Thanks!
That's very helpful

I started another post on a similar varying width theme.
You're all invited to help...

https://www.edaboard.com/threads/263758/

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Will the following "LSB first shift right register" synthesize correctly ?

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