Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to calculate the pattern noise in sig-del modulator?

Status
Not open for further replies.

Hughes

Advanced Member level 3
Joined
Jun 10, 2003
Messages
715
Helped
113
Reputation
226
Reaction score
26
Trophy points
1,298
Activity points
5,984
The attached figure from Fernando Medeiro's book: "Top-Down Design of High-Performance Sigma-Delta Modulators". It is about pattern noise for a first-order Sigma-Delta modulator with oversampling ratio M=64. The horizontal axis is "DC input level refered to Del/2". The Vertical axis is "in-band quantization error power(dB)."

But I don't know how to get such a figure by simulation. Any can help me? Thank in advance.
 

PLease reference on which page in the book this figure comes - I'll have a look in the evening, maybe I can help you with it..
 

    Hughes

    Points: 2
    Helpful Answer Positive Rating
Thank borodenkov.

The figure is on page 19, section 2.2.4 "Pattern-noise generation. Fernando didn't discuss much of this topic in his book. The figure was actually from one of his reference:
J. C. Candy and G. C. Temes, "Oversampling Delta-Sigma Converters", IEEE Press, 1992.

But I don't have this book.
 

Well, as far as I understood...

They apply a DC input (a constant value) to the input of the 1st modulator and look at its output. The modulator tries to average the input value and the output is a repetetative sequence - the quantization noise is not white but highly correlated with the input. The output PSD will have idle tones because the sequence has periodicity. The problem is that the quantization noise depends on the valur of the input (as shown in the figure). And the value of the noise power for some DC input values is much higher than the normally used prediction of Eq. 2.11. That means that the SNR and resolution of the modulator is also signal-dependent and lower than predicted.

If you are interested about idle tones, read the 3rd Chapter in the Yellow book by Norsworthy et al

How to simulate: build a simple behavioral model in MatlabSimulink/C using time difference equantions (or delay and summation blocks in Simulink). Then calculate the power of the quantization noise (output_signal - input_signal) for different inputs

Alex.
 

    Hughes

    Points: 2
    Helpful Answer Positive Rating
by the way,did you know the threary of Delta-Sigma using for other fields,just as voltage regulator &voltage reference.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top