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WARNING:Xst:737 - Found 1-bit latch for signal

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hello,
how can I remove
warnings
Code: 
WARNING:Xst:737 - Found 1-bit latch for signal <L_matrix_new<1><6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <L_matrix_new<1><5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <L_matrix_new<1><4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <L_matrix_new<1><3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <L_matrix_new<1><2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <L_matrix_new<1><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <L_matrix_new<1><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1293 - FF/Latch <out_a_2> has a constant value of 0 in block <total_00>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <sign_value_i<7>_0> has a constant value of 1 in block <total_00>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <sign_value_i<6>_0> has a constant value of 1 in block <total_00>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <sign_value_i<5>_0> has a constant value of 1 in block <total_00>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <sign_value_i<4>_0> has a constant value of 1 in block <total_00>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <sign_value_i<3>_0> has a constant value of 1 in block <total_00>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <sign_value_i<2>_0> has a constant value of 1 in block <total_00>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <sign_value_i<1>_0> has a constant value of 1 in block <total_00>. This FF/Latch will be trimmed during the optimization process

WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<7><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<7><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<6><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<6><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<5><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<5><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<4><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<4><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<3><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<3><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<2><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_i<2><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.


parts of code
Code: 
sign_value_i(i2)<=1 when d>=0 else
                 -1;
      sign_each_row_new<=sign_value_i(1)*sign_value_i(2)*sign_value_i(3)*sign_value_i(4)*sign_value_i(5)*sign_value_i(6) when ((i2=6) and (length_row=7)) else
                         sign_value_i(1)*sign_value_i(2)*sign_value_i(3)*sign_value_i(4)*sign_value_i(5)*sign_value_i(6)*sign_value_i(7) when ((i2=7) and (length_row=8));      
      sign_value_new<=sign_value_i;
      
      c<=L_matrix_ii+d when i2/=7 else
         L_matrix_ii+d when i2=7 and length_row=8 else
          0;
          L_matrix_new(i2)<=c;

this warning"WARNING:Xst:1293 - FF/Latch <sign_value_i<1>_0> has a constant value of 1 in block <total_00>. This FF/Latch will be trimmed during the optimization process" is dangerous?
 
Last edited:

looks like you need to rewrite the first statement. Is d a signed or unsigned variable and what is its range? It would also be better to formalise the assignment. So if we assume that d is an unsigned integer (or is treated as one) with a range 0 to 255 then:

sign_value_i(i2 )<= 1 when (d > = 0 and d < 128) else - 1;

an alternative might be to set up a sequential process sensitive to d:

set_sign_val: process(d)
begin
if (d > = 0 and d < 128) then sign_value_i(i2 ) <= 1;
else sign_value_i(i2 ) <= - 1;
end
The latches are being generated because d is being treated as an unsigned number, therefore your statement just says the same as

sign_value_i(i2 ) <= 1; and never changes. you probably get similar warnings for all the other signals dependant on sign_value_i(i2 )

I suspect that sign_value_i(i2 ) may also be treated the same
 
The latches are because you have asynchronous code and incomplete statements. the "sign_each_new_row" value does not have an unconditional else clause, which is causing the latches. Not the constant value of sign_value_i like chipseller suggested. A constant value would probably make latches fall out.
 
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