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[SOLVED] Logic for implementing different statements at every rising edge.

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verylsi

verylsi

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Hey,

I was looking to implement different statements at every rising edge of a clock.

I can think of using a counter, incrementing at every rising edge of the clock and assigning different statements at every counter value using case statements.

Any better logic for better realization ?

Code: 
Process (clk) 
				Begin
				
				if rising_edge(clk) then 


						if count_x <= "111" then 
						
							count_x    <= "000";

						else 
						
							count_x    <=  count_x + 1;
					
						end if;
	
						
					end if;
				end process;
				
					
					
				Process (count_x )
				Begin
				
				if rising_edge(count_x(0)) then 
				
				case count_x is 
				
				when "001" =>
									
					SDA <= data_reg (0);
					
				when "010" =>
									
					SDA <= data_reg (1);
					
				when "011" =>
									
					SDA <= data_reg (2);

                                            when others => null ;

                                            end case;
                                            end process;

Cheers .
 

for this particular example, you can just use :

SDA <= data_reg ( conv_integer(count_x)-1 );
 

verylsi said:
Hey,

I was looking to implement different statements at every rising edge of a clock.

I can think of using a counter, incrementing at every rising edge of the clock and assigning different statements at every counter value using case statements.

Any better logic for better realization ?
Click to expand...

A simple shift register would be better in the case you posted.

Kevin Jennings
 

Thanks K J,

actually I am not able to use shift register, thats because I have to update the signal in different process and I need to shift it in different process, and updating the register and shifting it at different clocks gives me multisource error .
Can you give any solution to how to use shift register in such situations?

Thanks
 

Is it possible your input is not latched when sampled? do you want to only count occurrences of pulses on data? then latch on edge and clear when read. then you wont get aliasing. If these processes are not fast enough, use a Set reset flip flop. Data edge sets, then process read resets.

Of course if you want to execute different statements in a predetermined manner, then you want to design a Finite State Machine, which speaks volumes.
 
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    verylsi

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verylsi said:
Thanks K J,

actually I am not able to use shift register, thats because I have to update the signal in different process and I need to shift it in different process, and updating the register and shifting it at different clocks gives me multisource error .
Can you give any solution to how to use shift register in such situations?
Click to expand...

You cannot (repeat "cannot") have a signal driven from more than one process in any code that is intended to be synthesized. Therefore, you must use one process, and if the target device is an FPGA then that process should be clocked by a free running clock. Your shift register process is the troublemaker, you need to get that into the same process as the one that loads count_x. In particular, the troublemaker is the following:

if rising_edge(count_x(0)) then

- You don't want to have a process use the rising edge of some arbitrary logic signal. The synthesis tool will synthesize it just fine, you'll just be left scratching your head as to why the design "works sometimes, then stops", "works when it is cold, then stops", "works when it has warmed up, then stops".
- It is not necessary. To detect the rising edge on any logic signal, just compare it with the value it has on the previous clock...like this.

Code VHDL - [expand]
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process(clock)
begin
   if rising_edge(clock) then
      count_x0_dlyd <= count_x(0);
      if ((count_x0_dlyd = '0' and (count_x(0) = '1')) then
         -- Do whatever you want based on the 'rising_edge(count_x(0))
     else
         -- Do stuff that you want to do if there is no rising_edge(count_x(0)
     end if;
   end if;
end process;


Kevin Jennings
 
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