physical design interview Q

* What is .lib, LEF, DEF, .tf?
* What are placement blockages?

* What is a macro and standard cell?
* What is wire load model?
* What does SDC constraints has?
* What are the Input needs for your design?
* What is SDC constraint file contains?
* If the routing congestion exists between two macros, then what will you do?
* How will you place the macros?
* How will you decide the die size?

Buddy, Please search in the forum first before posting the questions!.

Before posting the questions, please read them carefully.

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* What does SDC constraints has?
* What is SDC constraint file contains?
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The above 2 questions are same. Why posting the same twice?

Hi,

Answer to the first question:-
.lib is logical libraries which provide timing and functionality information for standard cells and provide timing information from macrocells
.lef is physical libraries which contain physical information(height,width) of all standard,pad,macro cells
.DEF is design exchange format u will write DEF once u have done analysis with icc u can use the same files in cadance
.tf technology file,technology file is unique to each technology and it contains metal information(like name and number desigination of metallayers/vias,electrical characterstics of metal layers/vias,design rule characterstics of metal layers/vias (wire to wire spacing,wire width),units and precissions,colour and patterns for display

---------- Post added at 16:29 ---------- Previous post was at 16:25 ----------

Hi,

Answer to second question:-

Hard Blockagesrevents placing of standard cells near or corner edges of macros completely
soft Blockages:-In soft blockages buffers and invertors are placed for optimization

With Regards,
Raviteja.

---------- Post added at 16:31 ---------- Previous post was at 16:29 ----------

Macro is nothing but it also contains standard cells,standard cells are your basic logic gates(and,or,nand,nor,not,buffer,xor,xnor)

---------- Post added at 16:33 ---------- Previous post was at 16:31 ----------

Wireload models contains parasatic values and are three types

Top,Segamented,Enclosed

---------- Post added at 16:38 ---------- Previous post was at 16:33 ----------

The inputs to your design are

1.logical libraries
2.physical libraries
3.technology files
4.TLU+ files
5.Gatelevel netlist
6.SDC(Synopsys Design constraints)
These are the inputs to your design

---------- Post added at 16:40 ---------- Previous post was at 16:38 ----------

SDC contains clock latancy,clock uncrtainity,input delay,output delay,multi cycle path,false paths,half cycle paths,clock definition

Raviteja .. you're hired .. newbie go read :-D more questions **broken link removed**

Manually we will place macros

flylines
corner utillizations
anchor bound option
groups
side channel option
legal oriantation option

---------- Post added at 17:48 ---------- Previous post was at 16:43 ----------

Hi sunny,

Can you plz post some questions on physical design flow,i just want to check my knowledge as i am a fresher searching for job in VLSI Back end.....,

With Regards,
Raviteja

http://asic.co.in/Index_files/verilog_interview_questions.htm

eg from simple search result

Thank you sunny....,


With Regards,
Raviteja

hi

For first question .. Please see this .. its has few more formats also ...

https://vlsi-expert.blogspot.in/p/different-file-formats-file-extensions.html

---------- Post added at 12:10 ---------- Previous post was at 12:09 ----------

for SDC question ...

Please refer this .. SDC

---------- Post added at 12:12 ---------- Previous post was at 12:10 ----------

for wire load ...

refer this .. Wire load model