Differences between signals and variables in hardware

Dear All,

Can i Ask, how signals and variables be represented in a hardware? and what is the difference between them in a clocked process?
another question please, what is the difference between the combinational and sequential process?

thanks in advance.

Re: Signals vs Variables

variables and signals can represent any hardware.
if placed correctly, there may be no difference between variables and signals
a combinatorial process creates combinatorial logic. Ive never heard of a sequential process.

Re: Signals vs Variables

TrickyDicky said:

variables and signals can represent any hardware.
if placed correctly, there may be no difference between variables and signals
a combinatorial process creates combinatorial logic. Ive never heard of a sequential process.

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Thanks TrickyDicky for your reply, but i means in my question that which component represents the signal or the variable indeed in a hardware device.
for the sequential process, i was asked this question "the difference between the combinational and sequential processes" in an interview, and i couldn't answer it.

thanks again.

Re: Signals vs Variables

With "sequential process" they probably mean a process that contain memory elements (registers or latches). This means that the outputs not only depend on the input signals, but also on what has happened previously.
The outputs from a combinatorial process only depend on the input signals.

Re: Signals vs Variables

that is all right std_match, but you may help me in the first question. that is it, what is the difference between signal and variables in a hardware point of view please?
thanks so much.

Re: Signals vs Variables

I basically agree with TrickyDicky that the differences between signals and variables aren't primarly related to hardware properties. Both can represent registers or combinatorial logic, it depends on how they are used.

Regarding terns, a process is generally designated sequential code in constrast to concurrent code (outside a process). The oposite of a combinatorial process is a registered or clock sensitive process in my view.

The next point is to understand the basic behavioral difference between variables and signals in a process.

A variable takes to a new value immediately when assigned to it, a signal after the process has finished. Only variables can hold intermediate results that are used in following expressions. In this usage, they represent combinatorial logic. But variable can also hold a value between the end of an process and it's next evaluation pass. Then their behaviour isn't different from a signal, representing either a register (clock synchronous process) or a combinatorial term, including the option of combinatorial loop or latch (for a combinatorial process).

Re: Signals vs Variables

In hardware description languages like VHDL, a signal maps directly to a "wire" which could be the input or output of a combinatorial or sequential process. When writing your code you would explicitly set up the signal to be mapped to an input or output, such as: a <= b;. This could occur either instantaneously if a <= b occurs in a combinatorial process (outside of a clocked process, in HDL) or could occur on a clock edge, like in the common D flip flop process ( if rising_edge(clk) then a<=b

A variable is a concept found in a traditional programming language. Unlike a signal, there is no direct mapping between a variable and a hardware part. Variables can be useful at times by providing a simpler description of a complicated operation but I almost never use them, since I like to know exactly what I am mapping (and therefore use signals).

Signals and variables both eventually map to primitive hardware components (memory elements and combinatorial logic) but in different ways.

Re: Signals vs Variables

rhearty1 said:

A variable is a concept found in a traditional programming language. Unlike a signal, there is no direct mapping between a variable and a hardware part. Variables can be useful at times by providing a simpler description of a complicated operation but I almost never use them, since I like to know exactly what I am mapping (and therefore use signals).

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I also like to know exactly what Im mapping, but I generally work that out before I write the code. And I do often use variables, mainly when the scope remains local to a process, like an un-tapped pipeline or local counters. It saves the large amounts of extra signal declarations at the top of files.

Re: Signals vs Variables

TrickyDicky said:

I also like to know exactly what Im mapping, but I generally work that out before I write the code. And I do often use variables, mainly when the scope remains local to a process, like an un-tapped pipeline or local counters. It saves the large amounts of extra signal declarations at the top of files.

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The only thing you save is three extra lines, regardless of how many local things you're talking about. A variable declaration takes the same amount of typing as a signal declaration. If you want that signal to be local to some area in the architecture, use a block statement



Kevin Jennings