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How to translate this verilog code to vhdl code

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prakashvenugopal

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Hi,

How to translate this verilog code to vhdl code. Please do let me know.

reg [6:0] counter = 0;
wire enable1u66; // pixel-rate, single-cycle clock enable pulse

always @(posedge clk16M6) // generate single-cycle pixel-rate clock enable pulse
if (counter >= 54) // divide 16.6MHz by 55
counter <= 0;
else
counter <= counter + 1'b1;

// Assert the clock enable every 55 cycles, a pixel-rate pulse
assign enable1u66 = (counter == 7'd0);
Click to expand...

Thanks,
V. Prakash
 

Something like this (entity declaration omitted):
Code: 
use ieee.numeric_std.all;

***** some stuff deleted here *******

signal counter: unsigned(6 downto 0);
signal enable1u66: std_logic;

***** some stuff deleted here *******

process(clk16M6)
begin
  if rising_edge(clk16M6) then
    if counter >= 54 then
      counter <= to_unsigned(0, counter'length); -- or (others => '0')
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

enable1u66 <= '1' when counter = 0 else '0';

Your code will probably cause glitches on the enable1u66 signal.
That can be avoided by having it clocked, something like this:

Code: 
use ieee.numeric_std.all;

***** some stuff deleted here *******

signal counter: unsigned(6 downto 0);
signal enable1u66: std_logic;

***** some stuff deleted here *******

process(clk16M6)
begin
  if rising_edge(clk16M6) then
    enable1u66 <= '0';
    if counter >= 54 then
      counter <= to_unsigned(0, counter'length); -- or (others => '0')
      enable1u66 <= '1';
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

I have not compiled this, so there can be syntax errors.
 
Last edited:
The first bit of code should be fine. Because the source of the signal is synchronous (counter) unless you have lots and lots of logic in it you'll probably not have any problems (especially at 16.6MHz). It wont glitch either (glitches only occur with asynchronous sources).
 
Hi,

Thanks for your reply. Below verilog code is for generating dval and lval pulse.

Base oscillator clock = 16.6 mhz = clk16M6
Dval Pulse--> On time = 1.66 usec and off time = 1.66 usec (3.32 usec) continuously
Lval Pulse--> On time = 844.8 usec and off time = 145.2 usec continuously


reg [6:0] counter = 0;
wire enable1u66; // pixel-rate, single-cycle clock enable pulse

always @(posedge clk16M6) // generate single-cycle pixel-rate clock enable pulse
if (counter >= 54) // divide 16.6MHz by 55
counter <= 0;
else
counter <= counter + 1'b1;

// Assert the clock enable every 55 cycles, a pixel-rate pulse
assign enable1u66 = (counter == 7'd0);


--DVAL:

reg dval = 1; // dval output to external video data sources, roughly 301.82KHz (3.31325uS)

always @(posedge clk16M6) dval <= (counter < 28); // dval has 28/27 duty cycle

--LVAL:

reg lval = 0; // output to external video data sources -- ON for 256 pixels periods, OFF for 44 pixel periods
reg lvalstate = 0;
reg [7:0] lvalcount = 0;

always @(posedge clk16M6)
if (enable1u66)
case(lvalstate)
0: // Keep LVAL low for 44 cycles
if (lvalcount == 43) begin // LOW period is over
lvalstate <= 1;
lval <= 1;
lvalcount <= 0; // reset the counter
end else
lvalcount <= lvalcount + 1'b1;

1: // Keep LVAL high for 256 cycles
if (lvalcount == 255) begin // HIGH period is over
lvalstate <= 0;
lval <= 0;
lvalcount <= 0; // reset the counter
end else
lvalcount <= lvalcount + 1'b1;

endcase
Click to expand...

The entity of this vhdl code is clk16M6, dval and lval

some of the above verilog code is not able to understand by me which is marked in bold. Can you please clear this by changing that to vhdl code.?


Thanks,
V. Prakash
 

in VHAL, that would be:

Code: 
signal dval : boolean;

process(clk)
begin
  if rising_edge(clk) then
    dval <= (counter < 28);
  end if;
end process;

or if dval is a std_logic;

Code: 
process(clk)
begin
  if rising_edge(clk) then
    if counter < 28 then
      dval <= '1';
    else
      dval <= '0';
    end if;
  end if;
end process;
 

    V

    Points: 2
    Helpful Answer Positive Rating
Hi,


Base oscillator clock = 16.6 mhz = clk16M6
Dval Pulse--> On time = 1.66 usec and off time = 1.66 usec (3.32 usec) continuously
Lval Pulse--> On time = 849.92 usec and off time = 146.08 usec continuously

Below is the verilog code for the above pulse generation:

reg [6:0] counter = 0;
wire enable1u66; // pixel-rate, single-cycle clock enable pulse

always @(posedge clk16M6) // generate single-cycle pixel-rate clock enable pulse
if (counter >= 54) // divide 16.6MHz by 55
counter <= 0;
else
counter <= counter + 1'b1;

// Assert the clock enable every 55 cycles, a pixel-rate pulse
assign enable1u66 = (counter == 7'd0);


--DVAL:

reg dval = 1; // dval output to external video data sources, roughly 301.82KHz (3.31325uS)

always @(posedge clk16M6) dval <= (counter < 28); // dval has 28/27 duty cycle

--LVAL:

reg lval = 0; // output to external video data sources -- ON for 256 pixels periods, OFF for 44 pixel periods
reg lvalstate = 0;
reg [7:0] lvalcount = 0;

always @(posedge clk16M6)
if (enable1u66)
case(lvalstate)
0: // Keep LVAL low for 44 cycles
if (lvalcount == 43) begin // LOW period is over
lvalstate <= 1;
lval <= 1;
lvalcount <= 0; // reset the counter
end else
lvalcount <= lvalcount + 1'b1;

1: // Keep LVAL high for 256 cycles
if (lvalcount == 255) begin // HIGH period is over
lvalstate <= 0;
lval <= 0;
lvalcount <= 0; // reset the counter
end else
lvalcount <= lvalcount + 1'b1;

endcase
Click to expand...


VHDL Code for the above verilog code is:

entity pulse_generation is
port ( clk16M6 : in std_logic;
dval: out std_logic;
lval: out std_logic := 0);
end pulse_generation;


architecture Behavioral of pulse_generation is

signal counter: unsigned(6 downto 0);
signal enable1u66: std_logic;
signal lvalstate: std_logic := '0';
signal lvalcount : std_logic_vector(7 downto 0) := "00000000";

begin

process(clk16M6)
begin
if rising_edge(clk16M6) then
enable1u66 <= '0';
if counter >= 54 then
counter <= "0000000"
enable1u66 <= '1';
else
counter <= counter + 1;
end if;
end if;
end process;


-- dval generation
process(clk16M6)
begin
if rising_edge(clk) then
if counter < 28 then
dval <= '1';
else
dval <= '0';
end if;
end if;
end process;

--lval generation
process(clk16M6)
if (enable1u66 = '1')
case(lvalstate)
0: -- Keep LVAL low for 44 cycles
if (lvalcount == 43) begin -- LOW period is over
lvalstate <= 1;
lval <= 1;
lvalcount <= "00000000"; -- reset the counter
end else
lvalcount <= lvalcount + 1;
end if;


1: -- Keep LVAL high for 256 cycles
if (lvalcount == 255) begin -- HIGH period is over
lvalstate <= 0;
lval <= 0;
lvalcount <= 0; -- reset the counter
end else
lvalcount <= lvalcount + 1;
end if;
end if;

endcase;
end behavioural;
Click to expand...

Please check the vhdl code for lval generation part marked in bold is correct. Having some error in this part.
Please check and let me know this lval generation is ok?

Thanks,
V. Prakash
 

Hi,

How to translate this verilog code to vhdl code:

reg lval = 0; // output to external video data sources -- ON for 256 pixels periods, OFF for 44 pixel periods
reg lvalstate = 0;
reg [7:0] lvalcount = 0;

always @(posedge clk16M6)
if (enable1u66)
case(lvalstate)
0: // Keep LVAL low for 44 cycles
if (lvalcount == 43) begin // LOW period is over
lvalstate <= 1;
lval <= 1;
lvalcount <= 0; // reset the counter
end else
lvalcount <= lvalcount + 1'b1;

1: // Keep LVAL high for 256 cycles
if (lvalcount == 255) begin // HIGH period is over
lvalstate <= 0;
lval <= 0;
lvalcount <= 0; // reset the counter
end else
lvalcount <= lvalcount + 1'b1;

endcase
Click to expand...

Thanks,
V. Prakash
 

It looks like you have forgotten VHDL syntax rules after reading Verilog.

Please check VHDL syntax for
- case construct
- if then
- std_logic constants
- compare operator

In addition use unsigned type for lvalcount
 

Hi FVM,

Thanks for the reply. i will check the VHDL construct syntax in the lval generation part and get back to you.

Thanks,
V. Prakash.
 

Hi,
I had changed the verilog code to vhdl code as below. It is found working.


process(clock)
begin
if clock = '1' and clock'event then
if (enable1u66 = '1') then
case(lvalstate) is
when '0' => -- Keep LVAL low for 44 cycles
if (lvalcount = 43) then -- LOW period is over
lvalstate <= '1';
lval <= '1';
lvalcount <= "00000000"; -- reset the counter
else lvalcount <= lvalcount + 1;
end if;

when '1' => -- Keep LVAL high for 256 cycles
if (lvalcount = 255) then --HIGH period is over
lvalstate <= '0';
lval <= '0';
lvalcount <= "00000000"; -- reset the counter
else lvalcount <= lvalcount + 1;
end if;

when others =>
lvalcount <= "00000000";
end case;
end if;
end if;
end process;

Thanks,
V. Prakash
 

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