Buffers/Inverters in clock path: Delay vs signal strength

Hi there,

In a typical clocked network with CMOS buffers as shown in the attached figure, I understand that buffers are inserted to improve signal strength. This is because, when the clock signal slowly dies as it travels, the supply voltage connected to the nmos(or pmos) of the buffer pulls it back to its original signal value (as long as the input voltage is greater(or less) than the threshold voltage of the nmos(or pmos)). Am I right? Please let me know if there is any other reason for inserting buffers

But on the other hand, because of the parasitic gate capacitances associated with the buffer, it introduces a delay in the clock signal as well. Is that right? On one hand, it is good as it provides a fix to hold time violation by some amount, but doesn't it increase the clock skew as well?

That's what confuses me. Could you please clarify? Also, I would appreciate if you could point out any mistake in my analysis.

Thanks in advance,
Rohit

hey Rohit,

You are analyzing in right direction, but a few things which are need to be looked with different perspective.

Here is a pdf, which has very good analysis of this problem https://courses.ece.ubc.ca/579/clockflop.pdf

Dear Rohit

In Deep Sub Micron Technology the impact if Interconnects parasitic Resistors and capacitors are dominant and the buffer insertion in clock tree increase speed and strength of the clock signals in the circuits. The Buffer insertion has an optimum point which the parasitic capacitance not to eliminate usefulness of the buffers in the clock routs.

I hope i could help you.
BR

rohit_singh1 said:

Hi there,

In a typical clocked network with CMOS buffers as shown in the attached figure, View attachment 66531 I understand that buffers are inserted to improve signal strength. This is because, when the clock signal slowly dies as it travels, the supply voltage connected to the nmos(or pmos) of the buffer pulls it back to its original signal value (as long as the input voltage is greater(or less) than the threshold voltage of the nmos(or pmos)). Am I right? Please let me know if there is any other reason for inserting buffers

But on the other hand, because of the parasitic gate capacitances associated with the buffer, it introduces a delay in the clock signal as well. Is that right? On one hand, it is good as it provides a fix to hold time violation by some amount, but doesn't it increase the clock skew as well?

That's what confuses me. Could you please clarify? Also, I would appreciate if you could point out any mistake in my analysis.

Thanks in advance,
Rohit

Click to expand...

You are right in the buffers adding delay to the path. But for hold fixing, we don't touch the clock paths. We add delay buffers to the data path and not clock path .