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ee1

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Hi,
After placement i see setup violations around 0-180 ns,
Should i continue to cts? Or if i am having these before cts they would only get worst?
Thanks!
 

Hi,
After placement i see setup violations around 0-180 ns,
Should i continue to cts? Or if i am having these before cts they would only get worst?
Thanks!

180ns ?? There is no way you can fix these after clock. Check your constraints file and make sure you have constrained properly or you have set all the false paths and multicycle paths properly.
 
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    ee1

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I agree with jeevan. Ideally you should fix all your setup violation before proceeding to CTS. 180ns is HUGE. I think there is some problem with your SDC. Can you tell me your operating frequency and technology.?
 
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    ee1

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My mistake.. I have 0.17ns=170ps...
 

No... From the beggining i had 170ps after placement, i miswritten 170ns...
 

During placement tool just places cells and doesn't do any optimization. So run a prects optimization using optDesign -preCTS. Your timing will improve.
 
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    ee1

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optDesign -preCTS?

i am using Synopsys Ic Compiler...
 

You can give CTS a try since useful skew and placement can improve your timing. But I don't suggest it. 170ps should be fine enough to proceed.
 
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    ee1

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Hi ee1,

You have mentioned about 170ps of violation in place-opt stage.

1) First check the violation is existing between valid half cycle path. (leading edge to trailing edge path or vice-versa)
2) If its not an valid half cycle path and its a genuine full cycle path only, try an incremental optimization on already optimized placement database. If this is also not yielding go for some floorplan changes or grouping of critical modules if any needed.

3) If the violation exist between half cycle path you may see this violation. These violation goes off post-cts.
4) The reason given below.
Assume the clock period of 2ns, setup time 150ps, uncertainity 200ps, datapath delay 1 ns

So Required time = 1 - 0.15 - 0.2 = 0.65ns (1 taken as clock period as it is a half cycle path)
Arrival Time (Datapath Delay = 1 ns

So Slack = -0.35 ns = 350ps.

During placement clock path is ideal and no delay is considered. When you do CTS, because of buffer addition, Latency will add to the clock path (Required time) and this violation will get fixed easily.


Regards,
Rajesh Srinivasa Rao
 

Hi ee1,

What is your TNS pre CTS. TNS is good measure as if you have handful of paths [with 170ps] there are advanced options in the tool to play with skew and fix the setup. If TNS is high it is good to fix at pre CTS.
 

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