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Re: multicycle path in soc.
the soc doesn't report any error,and say it read the multicycle successly.
Can you give any more hint about it ?
thank you very much.
I use soc to do apr, but It reported many violated. After read the report, I found it seems the soc encounter doesn't recognize the multicycle path constraint in dc script.
part of dc constrain
create_clock -name {CLK} -period 14.000000 \
waveform { 0.000000 7.000000 } [get_ports...
multicycle path in soc.
I use soc to do apr, but It reported many violated. After read the report, I found it seems the soc encounter doesn't recognize the multicycle path constraint in dc script.
part of dc constrain
create_clock -name {CLK} -period 14.000000 \
waveform {...
thanks for your reply.
the file :"/home/eda/synopsys/auxx/tcllib/snps_tcl/.ci_common.utils" does exist.
and i use bash..
For I can't find out the solution,so I update the os to rhel 4.0, and it works well now.
after install the product, and run dc-shell-t, the following error come out:
Initializing...
Error: couldn't read file "/home/eda/synopsys/auxx/tcllib/snps_tcl/.ci_common.utils": no such file or directory
Use error_info for more info. (CMD-013)
Error: unknown command 'setenv' (CMD-005)...
when I install ic5141 at redhat9.0, I follow gitarrelieber's article "How to install Cadence IC5.0.33 under Linux RedHat9", and the total time that i install ic5141 is more than 4 hours.;(
when I type icfb&, the following error comes out:
Incorrectly built binary which accesses errno or h_errno...
Re: script for STA
Advanced ASIC Chip Synthesis (2nd Ed, 2002)
have some scipts.
the primetime workshop, have lab guide,but no lab material.
If anyone finds the lab material,please upload. Thanks very much.
hi members,there is a dft question about the section in the book:
advanced asic chip synthesis,using snopsys design
compiler,physical compiler and prime time.
at the section :8.3.8 Logic Un-Scannable due to Memory Element
the author suggests that shortcircuiting all the inputs...
set_disable_timing
hi members, I am puzzled about when and why to set_disable_timing or set_false_path. For example,here is a figure in the book" advanced asis chip synthesis(2nd)".
the author suggests that we should use dc_shell command :
set_disable_timing U1 -from A -to Z
to disable the...
synopsys case parallel
how did you carry the test?In the following situation:
case (4b'sel)
1???:statement;
?1??:statement;
??1?:statement;
???1:statement;
defalt:statement;
endcase.
Is the result same whether with the parallel case directive or not?
Since my software's version is older, I...
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