[question]multicycle path in soc.

[zzczx]

I use soc to do apr, but It reported many violated. After read the report, I found it seems the soc encounter doesn't recognize the multicycle path constraint in dc script.

part of dc constrain

create_clock -name {CLK} -period 14.000000 \	
          waveform { 0.000000 7.000000 } [get_ports {clk}]     
set_input_delay -max 8.700000 -clock {CLK} [get_ports {da}]               
set_input_delay -min 7.000000 -clock {CLK} -add_delay \
           [get_ports{da}]    
set_multicycle_path 2 -setup -end    -from [get_clocks {CLK}] \
    -through [get_ports {da}] 
set_output_delay -max 8.000000 -clock {CLK} [get_ports {db}]              
set_output_delay -min 6.000000 -clock {CLK} -add_delay [get_ports {db}]

soc's report

Path #: 1
Startpoint: da
            (clocked by CLK R)
Endpoint: db
          (clocked by CLK R)
Data required time: 13.400 (minus uncertainty: 0.600 adjusted 1 cycle)
                                                        ~~~~~~~~~~~
                                                         it said 1 cycle ????

Data arrival time: 18.856
Slack: -5.456 (VIOLATED) 
Object name         Delta r/f (ns)  Sum r/f (ns)        Slew (ns)       Load (pf)  Cell Location (um) 
--------------------------------------------------------------------------------------------------------------------------
da  "set_input_delay"                  8.700f/8.700r   8.700f/8.700r       
da                                    0.055f/0.055r   8.755f/8.755r       2.900f/2.900r   
u15 A->Y (INVX8)                        0.758r/0.300f   9.514r/9.055f       2.900f/2.900r   0.236     (164.40, 123.40)    
n163                                    0.004r/0.004f   9.517r/9.059f       
u16 B->Y (NOR2X4)                       0.267f/0.500r   9.784f/9.559r       0.669f/0.741r   0.203     (177.00, 161.80)    
n164                                    0.005f/0.005r   9.789f/9.564r       
u20 A1->Y (AOI22X2)                     0.431r/0.115f   10.220r/9.678f      0.703f/0.965r   0.020     (298.50, 181.00)    
n166                                    0.000r/0.000f   10.220r/9.678f      
u21 B0->Y (OAI2BB1X2)                   0.076f/0.302r   10.296f/9.980r      0.688f/0.700r   0.017     (259.80, 161.80)    
db                                         0.000f/0.000r   10.296f/9.980r      
FE_OFC0_yc_mod_1_ A->Y (BUFX8)          0.242f/0.263r   10.538f/10.243r     0.185f/0.291r   0.149     (266.10, 161.80)    
FE_OFN0_yc_mod_1_                       0.004f/0.004r   10.542f/10.247r     
u22 A->Y (AND2X4)                       0.311f/0.348r   10.853f/10.594r     0.154f/0.261r   0.109     (138.30, 251.40)    
db                                       0.003f/0.003r   10.856f/10.597r     
db "set_output_delay"                       8.000f/8.000r   18.856f/18.597r

plz help me to solve this problem. thx