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In one design, there are both posedge and negedge FFs. for the dft design, if i want to put all the negedge FFs at the begining of the scan chain, how can i make the constrain in the script?
tetramax unsupported construct
When i read in the library model netlist, it reports that there are unsupported construct. and then there are a lot of Unconnected module internal nets
What should i do with such problem? thx
i have a question about the 2nd solution. Will it cause other timing violations for a synchronous design ? when we do the dc, don't we think the clock network is ideal?
But the problem is thate when i use the same gate netlist and the rtl netlist of that block and use the same settings to verify them separatly, not in hierarchy, they all passed and reported no failing points.
Hi,
I want to use formality to do the hierarchy verification for my design, so i use the write_hirearchical_verification_script command to write out a script, and then i source the scritp. The result told me that there is a block failed and this cause the higher hiearachical block...
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